+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
*/
#include <common.h>
+#include <clock_legacy.h>
+#include <command.h>
#include <div64.h>
+#include <init.h>
+#include <net.h>
#include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
#endif
#include <netdev.h>
+#include <spl.h>
#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
- fi *=
- decode_pll(readl(&ccm->mpctl),
- CONFIG_MX35_HCLK_FREQ);
+ fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
return fi / (arm_div * fd);
}
(struct ccm_regs *)IMX_CCM_BASE;
u32 pdr4 = readl(&ccm->pdr4);
- if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U) {
+ if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
freq = get_mcu_main_clk();
- } else {
- freq = decode_pll(readl(&ccm->ppctl),
- CONFIG_MX35_HCLK_FREQ);
- }
+ else
+ freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
freq /= CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_UART_PODF_MASK,
MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
break;
case USB_CLK:
usb_podf = (reg4 >> 22) & 0x3F;
- if (reg4 & 0x200) {
+ if (reg4 & 0x200)
pll = get_mcu_main_clk();
- } else {
- pll = decode_pll(readl(&ccm->ppctl),
- CONFIG_MX35_HCLK_FREQ);
- }
+ else
+ pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
ret_val = pll / (usb_podf + 1);
break;
clk_sel = mpdr3 & (1 << 14);
pdf = (mpdr4 >> 10) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
- (pdf + 1);
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case SSI1_BAUD:
pre_pdf = (mpdr2 >> 24) & 0x7;
pdf = mpdr2 & 0x3F;
clk_sel = mpdr2 & (1 << 6);
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case SSI2_BAUD:
pdf = (mpdr2 >> 8) & 0x3F;
clk_sel = mpdr2 & (1 << 6);
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case CSI_BAUD:
clk_sel = mpdr2 & (1 << 7);
pdf = (mpdr2 >> 16) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
- (pdf + 1);
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case MSHC_CLK:
pre_pdf = readl(&ccm->pdr1);
pdf = (pre_pdf >> 22) & 0x3F;
pre_pdf = (pre_pdf >> 28) & 0x7;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case ESDHC1_CLK:
clk_sel = mpdr3 & 0x40;
pdf = mpdr3 & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
- (pdf + 1);
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case ESDHC2_CLK:
clk_sel = mpdr3 & 0x40;
pdf = (mpdr3 >> 8) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
- (pdf + 1);
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case ESDHC3_CLK:
clk_sel = mpdr3 & 0x40;
pdf = (mpdr3 >> 16) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
- (pdf + 1);
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case SPDIF_CLK:
clk_sel = mpdr3 & 0x400000;
pre_pdf = (mpdr3 >> 29) & 0x7;
pdf = (mpdr3 >> 23) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
- decode_pll(readl(&ccm->ppctl), CONFIG_MX35_HCLK_FREQ)) /
+ decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
default:
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_IPG_PERCLK:
+ case MXC_I2C_CLK:
return get_ipg_per_clk();
case MXC_UART_CLK:
return imx_get_uartclk();
- case MXC_ESDHC_CLK:
+ case MXC_ESDHC1_CLK:
return mxc_get_peri_clock(ESDHC1_CLK);
+ case MXC_ESDHC2_CLK:
+ return mxc_get_peri_clock(ESDHC2_CLK);
+ case MXC_ESDHC3_CLK:
+ return mxc_get_peri_clock(ESDHC3_CLK);
case MXC_USB_CLK:
return mxc_get_main_clock(USB_CLK);
case MXC_FEC_CLK:
}
#endif
-int do_mx35_showclocks(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
+int do_mx35_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
{
u32 cpufreq = get_mcu_main_clk();
printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
return rc;
}
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
int get_clocks(void)
{
-#ifdef CONFIG_FSL_ESDHC
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#ifdef CONFIG_FSL_ESDHC_IMX
+#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#else
+ gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+#endif
#endif
return 0;
}
-void reset_cpu(ulong addr)
+#define RCSR_MEM_CTL_WEIM 0
+#define RCSR_MEM_CTL_NAND 1
+#define RCSR_MEM_CTL_ATA 2
+#define RCSR_MEM_CTL_EXPANSION 3
+#define RCSR_MEM_TYPE_NOR 0
+#define RCSR_MEM_TYPE_ONENAND 2
+#define RCSR_MEM_TYPE_SD 0
+#define RCSR_MEM_TYPE_I2C 2
+#define RCSR_MEM_TYPE_SPI 3
+
+u32 spl_boot_device(void)
{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
- writew(4, &wdog->wcr);
+ struct ccm_regs *ccm =
+ (struct ccm_regs *)IMX_CCM_BASE;
+
+ u32 rcsr = readl(&ccm->rcsr);
+ u32 mem_type, mem_ctl;
+
+ /* In external mode, no boot device is returned */
+ if ((rcsr >> 10) & 0x03)
+ return BOOT_DEVICE_NONE;
+
+ mem_ctl = (rcsr >> 25) & 0x03;
+ mem_type = (rcsr >> 23) & 0x03;
+
+ switch (mem_ctl) {
+ case RCSR_MEM_CTL_WEIM:
+ switch (mem_type) {
+ case RCSR_MEM_TYPE_NOR:
+ return BOOT_DEVICE_NOR;
+ case RCSR_MEM_TYPE_ONENAND:
+ return BOOT_DEVICE_ONENAND;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+ case RCSR_MEM_CTL_NAND:
+ return BOOT_DEVICE_NAND;
+ case RCSR_MEM_CTL_EXPANSION:
+ switch (mem_type) {
+ case RCSR_MEM_TYPE_SD:
+ return BOOT_DEVICE_MMC1;
+ case RCSR_MEM_TYPE_I2C:
+ return BOOT_DEVICE_I2C;
+ case RCSR_MEM_TYPE_SPI:
+ return BOOT_DEVICE_SPI;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+ }
+
+ return BOOT_DEVICE_NONE;
}
projects / J-u-boot.git / blobdiff