Merge tag 'v2023.10-rc4' into next

[J-u-boot.git] / board / freescale / ls1021aqds / ls1021aqds.c

diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 2ca2bd990935da100f5a3fe38d18ad5bfa87175c..a618ce11a584a432b21fb94be6c24aaf73fd72be 100644 (file)
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -1,26 +1,31 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2019, 2021 NXP
  */
 
 #include <common.h>
+#include <clock_legacy.h>
+#include <fdt_support.h>
 #include <i2c.h>
+#include <init.h>
+#include <log.h>
 #include <asm/io.h>
 #include <asm/arch/immap_ls102xa.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/ls102xa_soc.h>
 #include <asm/arch/ls102xa_devdis.h>
+#include <asm/sections.h>
 #include <hwconfig.h>
 #include <mmc.h>
 #include <fsl_csu.h>
-#include <fsl_esdhc.h>
 #include <fsl_ifc.h>
-#include <fsl_sec.h>
 #include <spl.h>
 #include <fsl_devdis.h>
 #include <fsl_validate.h>
 #include <fsl_ddr.h>
+#include "../common/i2c_mux.h"
 #include "../common/sleep.h"
 #include "../common/qixis.h"
 #include "ls1021aqds_qixis.h"
@@ -97,6 +102,7 @@ int checkboard(void)
        return 0;
 }
 
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
 unsigned long get_board_sys_clk(void)
 {
        u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
@@ -121,7 +127,9 @@ unsigned long get_board_sys_clk(void)
        }
        return 66666666;
 }
+#endif
 
+#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
 unsigned long get_board_ddr_clk(void)
 {
        u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
@@ -136,19 +144,7 @@ unsigned long get_board_ddr_clk(void)
        }
        return 66666666;
 }
-
-int select_i2c_ch_pca9547(u8 ch)
-{
-       int ret;
-
-       ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-       if (ret) {
-               puts("PCA: failed to select proper channel\n");
-               return ret;
-       }
-
-       return 0;
-}
+#endif
 
 int dram_init(void)
 {
@@ -156,27 +152,16 @@ int dram_init(void)
         * When resuming from deep sleep, the I2C channel may not be
         * in the default channel. So, switch to the default channel
         * before accessing DDR SPD.
+        *
+        * PCA9547(0x77) mount on I2C1 bus
         */
-       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
        return fsl_initdram();
 }
 
-#ifdef CONFIG_FSL_ESDHC
-struct fsl_esdhc_cfg esdhc_cfg[1] = {
-       {CONFIG_SYS_FSL_ESDHC_ADDR},
-};
-
-int board_mmc_init(bd_t *bis)
-{
-       esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-
-       return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
-}
-#endif
-
 int board_early_init_f(void)
 {
-       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
 
 #ifdef CONFIG_TSEC_ENET
        /* clear BD & FR bits for BE BD's and frame data */
@@ -201,7 +186,7 @@ int board_early_init_f(void)
 void board_init_f(ulong dummy)
 {
 #ifdef CONFIG_NAND_BOOT
-       struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+       struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
        u32 porsr1, pinctl;
 
        /*
@@ -212,7 +197,7 @@ void board_init_f(ulong dummy)
        porsr1 = in_be32(&gur->porsr1);
        pinctl = ((porsr1 & ~(DCFG_CCSR_PORSR1_RCW_MASK)) |
                 DCFG_CCSR_PORSR1_RCW_SRC_I2C);
-       out_be32((unsigned int *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
+       out_be32((unsigned int *)(CFG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
                 pinctl);
 #endif
 
@@ -232,7 +217,7 @@ void board_init_f(ulong dummy)
 
        preloader_console_init();
 
-#ifdef CONFIG_SPL_I2C_SUPPORT
+#ifdef CONFIG_SPL_I2C
        i2c_init_all();
 #endif
 
@@ -250,7 +235,7 @@ void board_init_f(ulong dummy)
 
 void config_etseccm_source(int etsec_gtx_125_mux)
 {
-       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
 
        switch (etsec_gtx_125_mux) {
        case GE0_CLK125:
@@ -324,7 +309,7 @@ int config_board_mux(int ctrl_type)
 
 int config_serdes_mux(void)
 {
-       struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
+       struct ccsr_gur *gur = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR;
        u32 cfg;
 
        cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
@@ -403,9 +388,6 @@ int misc_init_r(void)
 
 #ifdef CONFIG_FSL_DEVICE_DISABLE
        device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
-#endif
-#ifdef CONFIG_FSL_CAAM
-       return sec_init();
 #endif
        return 0;
 }
@@ -419,7 +401,7 @@ int board_init(void)
        erratum_a009942_check_cpo();
 #endif
 
-       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
 
 #ifndef CONFIG_SYS_FSL_NO_SERDES
        fsl_serdes_init();
@@ -444,7 +426,7 @@ void board_sleep_prepare(void)
 }
 #endif
 
-int ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, struct bd_info *bd)
 {
        ft_cpu_setup(blob, bd);