* Copyright (C) 2018 Xilinx, Inc. (Michal Simek)
*/
-#include <common.h>
+#include <bootstage.h>
#include <dm.h>
#include <errno.h>
+#include <init.h>
#include <timer.h>
+#include <asm/global_data.h>
#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
#define CNT_CNTRL_RESET BIT(4)
struct cadence_ttc_regs *regs;
};
-static int cadence_ttc_get_count(struct udevice *dev, u64 *count)
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
+ulong timer_get_boot_us(void)
{
- struct cadence_ttc_priv *priv = dev_get_priv(dev);
+ u64 ticks = 0;
+ u32 rate = 1;
+ u64 us;
+ int ret;
+
+ ret = dm_timer_init();
+ if (!ret) {
+ /* The timer is available */
+ rate = timer_get_rate(gd->timer);
+ timer_get_count(gd->timer, &ticks);
+ } else {
+ return 0;
+ }
+
+ us = (ticks * 1000) / rate;
+ return us;
+}
+#endif
- *count = readl(&priv->regs->counter_val1);
+static u64 cadence_ttc_get_count(struct udevice *dev)
+{
+ struct cadence_ttc_priv *priv = dev_get_priv(dev);
- return 0;
+ return readl(&priv->regs->counter_val1);
}
static int cadence_ttc_probe(struct udevice *dev)
return 0;
}
-static int cadence_ttc_ofdata_to_platdata(struct udevice *dev)
+static int cadence_ttc_of_to_plat(struct udevice *dev)
{
struct cadence_ttc_priv *priv = dev_get_priv(dev);
return 0;
}
+static int cadence_ttc_bind(struct udevice *dev)
+{
+ const char *cells;
+
+ cells = dev_read_prop(dev, "#pwm-cells", NULL);
+ if (cells)
+ return -ENODEV;
+
+ return 0;
+}
+
static const struct timer_ops cadence_ttc_ops = {
.get_count = cadence_ttc_get_count,
};
.name = "cadence_ttc",
.id = UCLASS_TIMER,
.of_match = cadence_ttc_ids,
- .ofdata_to_platdata = cadence_ttc_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct cadence_ttc_priv),
+ .of_to_plat = cadence_ttc_of_to_plat,
+ .priv_auto = sizeof(struct cadence_ttc_priv),
.probe = cadence_ttc_probe,
.ops = &cadence_ttc_ops,
- .flags = DM_FLAG_PRE_RELOC,
+ .bind = cadence_ttc_bind,
};