Added 64-bit MMIO accessors for ARMv8

[J-u-boot.git] / include / configs / CPC45.h

diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h
index 91d262a22c659c49102c9acd86303d455f6944c2..a75c52f2c714f94957100c0025e9a8885b3e4615 100644 (file)
--- a/include/configs/CPC45.h
+++ b/include/configs/CPC45.h
@@ -2,23 +2,7 @@
  * (C) Copyright 2001-2005
  * Wolfgang Denk, DENX Software Engineering, [email protected].
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /*
@@ -41,14 +25,13 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC824X         1
 #define CONFIG_MPC8245         1
 #define CONFIG_CPC45           1
 
+#define CONFIG_SYS_TEXT_BASE   0xFFF00000
 
 #define CONFIG_CONS_INDEX      1
 #define CONFIG_BAUDRATE                9600
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 
 #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
 
@@ -90,15 +73,11 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP                    /* undef to save memory         */
-#define CONFIG_SYS_PROMPT      "=> "           /* Monitor Command Prompt       */
 #define CONFIG_SYS_CBSIZE      256             /* Console I/O Buffer Size      */
 
 #if 1
 #define CONFIG_SYS_HUSH_PARSER         1       /* use "hush" command parser    */
 #endif
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
-#endif
 
 /* Print Buffer Size
  */
@@ -126,7 +105,7 @@
 
 #define CONFIG_SYS_EUMB_ADDR           0xFCE00000
 
-#define CONFIG_SYS_MONITOR_BASE        TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 #define CONFIG_SYS_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
@@ -150,13 +129,9 @@
  * Definitions for initial stack pointer and data area
  */
 
-/* Size in bytes reserved for initial data
- */
-#define CONFIG_SYS_GBL_DATA_SIZE       128
-
 #define CONFIG_SYS_INIT_RAM_ADDR       0x40000000
-#define CONFIG_SYS_INIT_RAM_END        0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE       0x1000
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
  * NS16550 Configuration
@@ -203,7 +178,6 @@
  */
 
 #define CONFIG_SYS_CLK_FREQ    33000000
-#define CONFIG_SYS_HZ                  1000
 
 
 /* Bit-field values for MCCR1.
@@ -338,22 +312,11 @@
 #  define CONFIG_SYS_CACHELINE_SHIFT   5       /* log base 2 of the above value        */
 #endif
 
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD          0x01    /* Normal Power-On: Boot from FLASH     */
-#define BOOTFLAG_WARM          0x02    /* Software reboot                      */
-
-
-#define SRAM_BASE              0x80000000      /* SRAM base address    */
-#define SRAM_END               0x801FFFFF
-
 /*----------------------------------------------------------------------*/
 /* CPC45 Memory Map                                                    */
 /*----------------------------------------------------------------------*/
 #define SRAM_BASE      0x80000000      /* SRAM base address            */
+#define SRAM_END       0x801FFFFF
 #define ST16552_A_BASE 0x80200000      /* ST16552 channel A            */
 #define ST16552_B_BASE 0x80400000      /* ST16552 channel A            */
 #define BCSR_BASE      0x80600000      /* board control / status registers */
@@ -361,6 +324,8 @@
 #define PCMCIA_MEM_BASE 0x83000000     /* PCMCIA memory window base    */
 #define PCMCIA_IO_BASE 0xFE000000      /* PCMCIA IO window base        */
 
+#define        CONFIG_SYS_SRAM_BASE    SRAM_BASE
+#define        CONFIG_SYS_SRAM_SIZE    (SRAM_END - SRAM_BASE + 1)
 
 /*---------------------------------------------------------------------*/
 /* CPC45 Control/Status Registers                                     */
@@ -466,10 +431,11 @@
  *-----------------------------------------------------------------------
  */
 #define CONFIG_PCI                     /* include pci support                  */
+#define CONFIG_PCI_INDIRECT_BRIDGE     /* indirect PCI bridge support */
+#define CONFIG_SYS_EARLY_PCI_INIT
 #undef CONFIG_PCI_PNP
 #undef CONFIG_PCI_SCAN_SHOW
 
-#define CONFIG_NET_MULTI               /* Multi ethernet cards support         */
 
 #define CONFIG_EEPRO100
 #define CONFIG_SYS_RX_ETH_BUFFER       8       /* use 8 rx buffer on eepro100  */
@@ -496,6 +462,7 @@
  *-----------------------------------------------------------------------
  */
 
+#define CONFIG_IDE_PREINIT     1       /* Use preinit IDE hook */
 #define        CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 
 #undef CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */