microblaze: Enable cache by default

[J-u-boot.git] / include / sdhci.h

diff --git a/include/sdhci.h b/include/sdhci.h
index fdef7c40c9a929cc0b743d5a1e34ec24df3d117c..01addb7a6036585606179a2257dca0233475b67d 100644 (file)
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -1,9 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2011, Marvell Semiconductor Inc.
  * Lei Wen <[email protected]>
  *
- * SPDX-License-Identifier:    GPL-2.0+
- *
  * Back ported to the 8xx platform (from the 8260 platform) by
  * [email protected], 27-Jan-01.
  */
@@ -145,7 +144,23 @@
 
 #define SDHCI_ACMD12_ERR       0x3C
 
-/* 3E-3F reserved */
+#define SDHCI_HOST_CONTROL2    0x3E
+#define  SDHCI_CTRL_UHS_MASK   0x0007
+#define  SDHCI_CTRL_UHS_SDR12  0x0000
+#define  SDHCI_CTRL_UHS_SDR25  0x0001
+#define  SDHCI_CTRL_UHS_SDR50  0x0002
+#define  SDHCI_CTRL_UHS_SDR104 0x0003
+#define  SDHCI_CTRL_UHS_DDR50  0x0004
+#define  SDHCI_CTRL_HS400      0x0005 /* Non-standard */
+#define  SDHCI_CTRL_VDD_180    0x0008
+#define  SDHCI_CTRL_DRV_TYPE_MASK      0x0030
+#define  SDHCI_CTRL_DRV_TYPE_B 0x0000
+#define  SDHCI_CTRL_DRV_TYPE_A 0x0010
+#define  SDHCI_CTRL_DRV_TYPE_C 0x0020
+#define  SDHCI_CTRL_DRV_TYPE_D 0x0030
+#define  SDHCI_CTRL_EXEC_TUNING        0x0040
+#define  SDHCI_CTRL_TUNED_CLK  0x0080
+#define  SDHCI_CTRL_PRESET_VAL_ENABLE  0x8000
 
 #define SDHCI_CAPABILITIES     0x40
 #define  SDHCI_TIMEOUT_CLK_MASK        0x0000003F
@@ -167,6 +182,11 @@
 #define  SDHCI_CAN_64BIT       BIT(28)
 
 #define SDHCI_CAPABILITIES_1   0x44
+#define  SDHCI_SUPPORT_SDR50   0x00000001
+#define  SDHCI_SUPPORT_SDR104  0x00000002
+#define  SDHCI_SUPPORT_DDR50   0x00000004
+#define  SDHCI_USE_SDR50_TUNING        0x00002000
+
 #define  SDHCI_CLOCK_MUL_MASK  0x00FF0000
 #define  SDHCI_CLOCK_MUL_SHIFT 16
 
@@ -182,6 +202,7 @@
 /* 55-57 reserved */
 
 #define SDHCI_ADMA_ADDRESS     0x58
+#define SDHCI_ADMA_ADDRESS_HI  0x5c
 
 /* 60-FB reserved */
 
@@ -213,8 +234,15 @@
 #define SDHCI_QUIRK_BROKEN_R1B         (1 << 2)
 #define SDHCI_QUIRK_NO_HISPD_BIT       (1 << 3)
 #define SDHCI_QUIRK_BROKEN_VOLTAGE     (1 << 4)
+/*
+ * SDHCI_QUIRK_BROKEN_HISPD_MODE
+ * the hardware cannot operate correctly in high-speed mode,
+ * this quirk forces the sdhci host-controller to non high-speed mode
+ */
+#define SDHCI_QUIRK_BROKEN_HISPD_MODE  BIT(5)
 #define SDHCI_QUIRK_WAIT_SEND_CMD      (1 << 6)
 #define SDHCI_QUIRK_USE_WIDE8          (1 << 8)
+#define SDHCI_QUIRK_NO_1_8_V           (1 << 9)
 
 /* to make gcc happy */
 struct sdhci_host;
@@ -235,9 +263,44 @@ struct sdhci_ops {
 #endif
        int     (*get_cd)(struct sdhci_host *host);
        void    (*set_control_reg)(struct sdhci_host *host);
+       int     (*set_ios_post)(struct sdhci_host *host);
        void    (*set_clock)(struct sdhci_host *host, u32 div);
+       int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
+       void (*set_delay)(struct sdhci_host *host);
 };
 
+#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
+#define ADMA_MAX_LEN   65532
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+#define ADMA_DESC_LEN  16
+#else
+#define ADMA_DESC_LEN  8
+#endif
+#define ADMA_TABLE_NO_ENTRIES (CONFIG_SYS_MMC_MAX_BLK_COUNT * \
+                              MMC_MAX_BLOCK_LEN) / ADMA_MAX_LEN
+
+#define ADMA_TABLE_SZ (ADMA_TABLE_NO_ENTRIES * ADMA_DESC_LEN)
+
+/* Decriptor table defines */
+#define ADMA_DESC_ATTR_VALID           BIT(0)
+#define ADMA_DESC_ATTR_END             BIT(1)
+#define ADMA_DESC_ATTR_INT             BIT(2)
+#define ADMA_DESC_ATTR_ACT1            BIT(4)
+#define ADMA_DESC_ATTR_ACT2            BIT(5)
+
+#define ADMA_DESC_TRANSFER_DATA                ADMA_DESC_ATTR_ACT2
+#define ADMA_DESC_LINK_DESC    (ADMA_DESC_ATTR_ACT1 | ADMA_DESC_ATTR_ACT2)
+
+struct sdhci_adma_desc {
+       u8 attr;
+       u8 reserved;
+       u16 len;
+       u32 addr_lo;
+#ifdef CONFIG_DMA_ADDR_T_64BIT
+       u32 addr_hi;
+#endif
+} __packed;
+#endif
 struct sdhci_host {
        const char *name;
        void *ioaddr;
@@ -258,6 +321,17 @@ struct sdhci_host {
        uint    voltages;
 
        struct mmc_config cfg;
+       dma_addr_t start_addr;
+       int flags;
+#define USE_SDMA       (0x1 << 0)
+#define USE_ADMA       (0x1 << 1)
+#define USE_ADMA64     (0x1 << 2)
+#define USE_DMA                (USE_SDMA | USE_ADMA | USE_ADMA64)
+       dma_addr_t adma_addr;
+#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
+       struct sdhci_adma_desc *adma_desc_table;
+       uint desc_slot;
+#endif
 };
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
@@ -409,9 +483,11 @@ int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
 #endif /* !CONFIG_BLK */
 
-#ifdef CONFIG_DM_MMC_OPS
+void sdhci_set_uhs_timing(struct sdhci_host *host);
+#ifdef CONFIG_DM_MMC
 /* Export the operations to drivers */
 int sdhci_probe(struct udevice *dev);
+int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
 extern const struct dm_mmc_ops sdhci_ops;
 #else
 #endif