soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driver

[J-u-boot.git] / drivers / spi / cf_spi.c

diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c
index 8fa6d35107561ed2564d06b18965d2cad2c3d959..6511c0e0e541707bb853072f38fdc9d68e77c9e3 100644 (file)
--- a/drivers/spi/cf_spi.c
+++ b/drivers/spi/cf_spi.c
@@ -16,6 +16,7 @@
 #include <common.h>
 #include <dm.h>
 #include <log.h>
+#include <asm/global_data.h>
 #include <dm/platform_data/spi_coldfire.h>
 #include <spi.h>
 #include <malloc.h>
@@ -114,8 +115,8 @@ static int coldfire_spi_claim_bus(struct udevice *dev)
        struct udevice *bus = dev->parent;
        struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
        struct dspi *dspi = cfspi->regs;
-       struct dm_spi_slave_platdata *slave_plat =
-               dev_get_parent_platdata(dev);
+       struct dm_spi_slave_plat *slave_plat =
+               dev_get_parent_plat(dev);
 
        if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
                return -1;
@@ -133,8 +134,8 @@ static int coldfire_spi_release_bus(struct udevice *dev)
        struct udevice *bus = dev->parent;
        struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
        struct dspi *dspi = cfspi->regs;
-       struct dm_spi_slave_platdata *slave_plat =
-               dev_get_parent_platdata(dev);
+       struct dm_spi_slave_plat *slave_plat =
+               dev_get_parent_plat(dev);
 
        /* Clear FIFO */
        clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
@@ -150,7 +151,7 @@ static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
 {
        struct udevice *bus = dev_get_parent(dev);
        struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
-       struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+       struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
        u16 *spi_rd16 = NULL, *spi_wr16 = NULL;
        u8 *spi_rd = NULL, *spi_wr = NULL;
        static u32 ctrl;
@@ -240,7 +241,7 @@ static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
        cfspi->baudrate = max_hz;
 
        /* Read current setup */
-       bus_setup = readl(&dspi->ctar[bus->seq]);
+       bus_setup = readl(&dspi->ctar[dev_seq(bus)]);
 
        tmp = (prescaler[3] * scaler[15]);
        /* Maximum and minimum baudrate it can handle */
@@ -294,7 +295,7 @@ static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz)
 
        bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f));
        bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
-       writel(bus_setup, &dspi->ctar[bus->seq]);
+       writel(bus_setup, &dspi->ctar[dev_seq(bus)]);
 
        return 0;
 }
@@ -318,7 +319,7 @@ static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
        if (cfspi->mode & SPI_MODE_MOD) {
                if ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) == 0)
                        bus_setup |=
-                           readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT;
+                           readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT;
                else
                        bus_setup |=
                            ((cfspi->mode & SPI_MODE_XFER_SZ_MASK) >> 1);
@@ -329,21 +330,21 @@ static int coldfire_spi_set_mode(struct udevice *bus, uint mode)
                bus_setup |= (cfspi->mode & SPI_MODE_DLY_SCA_MASK) >> 4;
        } else {
                bus_setup |=
-                       (readl(&dspi->ctar[bus->seq]) & MCF_CTAR_MODE_MASK);
+                       (readl(&dspi->ctar[dev_seq(bus)]) & MCF_CTAR_MODE_MASK);
        }
 
        cfspi->charbit =
-               ((readl(&dspi->ctar[bus->seq]) & MCF_FRM_SZ_16BIT) ==
+               ((readl(&dspi->ctar[dev_seq(bus)]) & MCF_FRM_SZ_16BIT) ==
                        MCF_FRM_SZ_16BIT) ? 16 : 8;
 
-       setbits_be32(&dspi->ctar[bus->seq], bus_setup);
+       setbits_be32(&dspi->ctar[dev_seq(bus)], bus_setup);
 
        return 0;
 }
 
 static int coldfire_spi_probe(struct udevice *bus)
 {
-       struct coldfire_spi_platdata *plat = dev_get_platdata(bus);
+       struct coldfire_spi_plat *plat = dev_get_plat(bus);
        struct coldfire_spi_priv *cfspi = dev_get_priv(bus);
        struct dspi *dspi = cfspi->regs;
        int i;
@@ -384,10 +385,10 @@ static int coldfire_spi_probe(struct udevice *bus)
 }
 
 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
-static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus)
+static int coldfire_dspi_of_to_plat(struct udevice *bus)
 {
        fdt_addr_t addr;
-       struct coldfire_spi_platdata *plat = bus->platdata;
+       struct coldfire_spi_plat *plat = dev_get_plat(bus);
        const void *blob = gd->fdt_blob;
        int node = dev_of_offset(bus);
        int *ctar, len;
@@ -451,10 +452,10 @@ U_BOOT_DRIVER(coldfire_spi) = {
        .id = UCLASS_SPI,
 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
        .of_match = coldfire_spi_ids,
-       .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,
-       .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),
+       .of_to_plat = coldfire_dspi_of_to_plat,
+       .plat_auto      = sizeof(struct coldfire_spi_plat),
 #endif
        .probe = coldfire_spi_probe,
        .ops = &coldfire_spi_ops,
-       .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),
+       .priv_auto      = sizeof(struct coldfire_spi_priv),
 };