#include <bouncebuf.h>
#include <common.h>
+#include <cpu_func.h>
#include <errno.h>
#include <malloc.h>
#include <memalign.h>
#include <mmc.h>
#include <dwmmc.h>
#include <wait_bit.h>
+#include <asm/cache.h>
+#include <power/regulator.h>
#define PAGE_SIZE 4096
dwmci_set_idma_desc(cur_idmac, flags, cnt,
(ulong)bounce_buffer + (i * PAGE_SIZE));
+ cur_idmac++;
if (blk_cnt <= 8)
break;
blk_cnt -= 8;
- cur_idmac++;
i++;
} while(1);
data_end = (ulong)cur_idmac;
- flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
+ flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN));
ctrl = dwmci_readl(host, DWMCI_CTRL);
ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
{
unsigned int timeout;
- timeout = size * 8 * 1000; /* counting in bits and msec */
- timeout *= 2; /* wait twice as long */
+ timeout = size * 8; /* counting in bits */
+ timeout *= 10; /* wait 10 times as long */
timeout /= mmc->clock;
timeout /= mmc->bus_width;
timeout /= mmc->ddr_mode ? 2 : 1;
+ timeout *= 1000; /* counting in msec */
timeout = (timeout < 1000) ? 1000 : timeout;
return timeout;
if (host->clksel)
host->clksel(host);
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+ if (mmc->vqmmc_supply) {
+ int ret;
+
+ if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
+ regulator_set_value(mmc->vqmmc_supply, 1800000);
+ else
+ regulator_set_value(mmc->vqmmc_supply, 3300000);
+
+ ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
+ if (ret)
+ return ret;
+ }
+#endif
+
return 0;
}