ARM: am3517_evm: Fix pin muxing to enable EHCI Host in the future

[J-u-boot.git] / include / ns16550.h

diff --git a/include/ns16550.h b/include/ns16550.h
index 0607379537d7ccf1038a0d322fdf29d95fbc0df4..22b89e4d6d19db7df724b1775d6aa386bc1c9818 100644 (file)
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -33,7 +33,7 @@
 
 #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
 #error "Please define NS16550 registers size."
-#elif defined(CONFIG_SYS_NS16550_MEM32)
+#elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL)
 #define UART_REG(x) u32 x
 #elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
 #define UART_REG(x)                                               \
@@ -49,13 +49,17 @@
  * struct ns16550_platdata - information about a NS16550 port
  *
  * @base:              Base register address
+ * @reg_width:         IO accesses size of registers (in bytes)
  * @reg_shift:         Shift size of registers (0=byte, 1=16bit, 2=32bit...)
  * @clock:             UART base clock speed in Hz
  */
 struct ns16550_platdata {
        unsigned long base;
+       int reg_width;
        int reg_shift;
+       int reg_offset;
        int clock;
+       u32 fcr;
 };
 
 struct udevice;
@@ -116,6 +120,14 @@ typedef struct NS16550 *NS16550_t;
 #define UART_FCR_RXSR          0x02 /* Receiver soft reset */
 #define UART_FCR_TXSR          0x04 /* Transmitter soft reset */
 
+/* Ingenic JZ47xx specific UART-enable bit. */
+#define UART_FCR_UME           0x10
+
+/* Clear & enable FIFOs */
+#define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \
+                       UART_FCR_RXSR | \
+                       UART_FCR_TXSR)
+
 /*
  * These are the definitions for the Modem Control Register
  */