Merge commit '53633a893a06bd5a0c807287d9cc29337806eaf7' as 'dts/upstream'

[J-u-boot.git] / drivers / fpga / virtex2.c

diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index 8871deaea6f6031c4366e6313859b2537730cce3..3ded27f9b3ffa4b88bed1710f3c1b0c385df6f21 100644 (file)
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -21,24 +21,21 @@
 #include <linux/delay.h>
 
 /*
- * If the SelectMap interface can be overrun by the processor, define
- * CONFIG_SYS_FPGA_CHECK_BUSY and/or CONFIG_FPGA_DELAY in the board
+ * If the SelectMap interface can be overrun by the processor, enable
+ * CONFIG_SYS_FPGA_CHECK_BUSY and/or define CFG_FPGA_DELAY in the board
  * configuration file and add board-specific support for checking BUSY status.
  * By default, assume that the SelectMap interface cannot be overrun.
  */
-#ifndef CONFIG_SYS_FPGA_CHECK_BUSY
-#undef CONFIG_SYS_FPGA_CHECK_BUSY
-#endif
 
-#ifndef CONFIG_FPGA_DELAY
-#define CONFIG_FPGA_DELAY()
+#ifndef CFG_FPGA_DELAY
+#define CFG_FPGA_DELAY()
 #endif
 
 /*
  * Check for errors during configuration by default
  */
-#ifndef CONFIG_SYS_FPGA_CHECK_ERROR
-#define CONFIG_SYS_FPGA_CHECK_ERROR
+#ifndef CFG_SYS_FPGA_CHECK_ERROR
+#define CFG_SYS_FPGA_CHECK_ERROR
 #endif
 
 /*
@@ -199,7 +196,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
        } while (!(*fn->init)(cookie));
 
        (*fn->pgm)(false, true, cookie);
-       CONFIG_FPGA_DELAY();
+       CFG_FPGA_DELAY();
        if (fn->clk)
                (*fn->clk)(true, true, cookie);
 
@@ -208,7 +205,7 @@ static int virtex2_slave_pre(xilinx_virtex2_slave_fns *fn, int cookie)
         */
        ts = get_timer(0);
        do {
-               CONFIG_FPGA_DELAY();
+               CFG_FPGA_DELAY();
                if (get_timer(ts) > CFG_SYS_FPGA_WAIT_INIT) {
                        printf("%s:%d: ** Timeout after %d ticks waiting for INIT to deassert.\n",
                               __func__, __LINE__, CFG_SYS_FPGA_WAIT_INIT);
@@ -236,7 +233,7 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
        /*
         * Finished writing the data; deassert FPGA CS_B and WRITE_B signals.
         */
-       CONFIG_FPGA_DELAY();
+       CFG_FPGA_DELAY();
        if (fn->cs)
                (*fn->cs)(false, true, cookie);
        if (fn->wr)
@@ -272,9 +269,9 @@ static int virtex2_slave_post(xilinx_virtex2_slave_fns *fn,
                        (*fn->wbulkdata)(&dummy, 1, true, cookie);
                } else {
                        (*fn->wdata)(0xff, true, cookie);
-                       CONFIG_FPGA_DELAY();
+                       CFG_FPGA_DELAY();
                        (*fn->clk)(false, true, cookie);
-                       CONFIG_FPGA_DELAY();
+                       CFG_FPGA_DELAY();
                        (*fn->clk)(true, true, cookie);
                }
        }
@@ -326,7 +323,7 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
                        break;
                }
 
-#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
+#ifdef CFG_SYS_FPGA_CHECK_ERROR
                if ((*fn->init)(cookie)) {
                        printf("\n%s:%d:  ** Error: INIT asserted during configuration\n",
                               __func__, __LINE__);
@@ -338,13 +335,13 @@ static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 #endif
 
                (*fn->wdata)(data[bytecount++], true, cookie);
-               CONFIG_FPGA_DELAY();
+               CFG_FPGA_DELAY();
 
                /*
                 * Cycle the clock pin
                 */
                (*fn->clk)(false, true, cookie);
-               CONFIG_FPGA_DELAY();
+               CFG_FPGA_DELAY();
                (*fn->clk)(true, true, cookie);
 
 #ifdef CONFIG_SYS_FPGA_CHECK_BUSY
@@ -461,7 +458,7 @@ static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
                                break;
                        }
 
-#ifdef CONFIG_SYS_FPGA_CHECK_ERROR
+#ifdef CFG_SYS_FPGA_CHECK_ERROR
                        if ((*fn->init)(cookie)) {
                                printf("\n%s:%d:  ** Error: INIT asserted during configuration\n",
                                       __func__, __LINE__);
@@ -475,9 +472,9 @@ static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
                        for (bit = 7; bit >= 0; --bit) {
                                unsigned char curr_bit = (curr_data >> bit) & 1;
                                (*fn->wdata)(curr_bit, true, cookie);
-                               CONFIG_FPGA_DELAY();
+                               CFG_FPGA_DELAY();
                                (*fn->clk)(false, true, cookie);
-                               CONFIG_FPGA_DELAY();
+                               CFG_FPGA_DELAY();
                                (*fn->clk)(true, true, cookie);
                        }