global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[J-u-boot.git] / board / freescale / ls1046afrwy / ls1046afrwy.c

diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c
index 41412a76b695620799a6f46a7a368014a1e6f838..f6e5c122ead6a2a8e21813ba190f03c605e0160f 100644 (file)
--- a/board/freescale/ls1046afrwy/ls1046afrwy.c
+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c
@@ -1,11 +1,13 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
  */
 
 #include <common.h>
 #include <i2c.h>
 #include <fdt_support.h>
+#include <init.h>
+#include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
@@ -18,13 +20,14 @@
 #include <fm_eth.h>
 #include <fsl_csu.h>
 #include <fsl_esdhc.h>
-#include <fsl_sec.h>
 #include <fsl_dspi.h>
+#include "../common/i2c_mux.h"
 
 #define LS1046A_PORSR1_REG 0x1EE0000
 #define BOOT_SRC_SD        0x20000000
 #define BOOT_SRC_MASK     0xFF800000
-#define BOARD_REV_GPIO         13
+#define BOARD_REV_GPIO_SHIFT   17
+#define BOARD_REV_MASK     0x03
 #define USB2_SEL_MASK     0x00000100
 
 #define BYTE_SWAP_32(word)  ((((word) & 0xff000000) >> 24) |  \
@@ -35,19 +38,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-int select_i2c_ch_pca9547(u8 ch)
-{
-       int ret;
-
-       ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
-       if (ret) {
-               puts("PCA: failed to select proper channel\n");
-               return ret;
-       }
-
-       return 0;
-}
-
 static inline void demux_select_usb2(void)
 {
        u32 val;
@@ -87,10 +77,14 @@ int board_early_init_f(void)
 
 static inline uint8_t get_board_version(void)
 {
-       u8 val;
        struct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);
 
-       val = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03;
+       /* GPIO 13 and GPIO 14 are used for Board Rev */
+       u32 gpio_val = ((in_be32(&pgpio->gpdat) >> BOARD_REV_GPIO_SHIFT))
+                               & BOARD_REV_MASK;
+
+       /* GPIOs' are 0..31 in Big Endiness, swap GPIO 13 and GPIO 14 */
+       u8 val = ((gpio_val >> 1) | (gpio_val << 1)) & BOARD_REV_MASK;
 
        return val;
 }
@@ -126,7 +120,7 @@ int checkboard(void)
 
 int board_init(void)
 {
-#ifdef CONFIG_SECURE_BOOT
+#ifdef CONFIG_NXP_ESBC
        /*
         * In case of Secure Boot, the IBR configures the SMMU
         * to allow only Secure transactions.
@@ -140,11 +134,7 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
        out_le32(SMMU_NSCR0, val);
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-       sec_init();
-#endif
-
-       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
        return 0;
 }
 
@@ -156,7 +146,7 @@ int board_setup_core_volt(u32 vdd)
 void config_board_mux(void)
 {
 #ifdef CONFIG_HAS_FSL_XHCI_USB
-       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
        u32 usb_pwrfault;
        /*
         * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT
@@ -199,7 +189,7 @@ int misc_init_r(void)
 }
 #endif
 
-int ft_board_setup(void *blob, bd_t *bd)
+int ft_board_setup(void *blob, struct bd_info *bd)
 {
        u64 base[CONFIG_NR_DRAM_BANKS];
        u64 size[CONFIG_NR_DRAM_BANKS];
@@ -214,7 +204,9 @@ int ft_board_setup(void *blob, bd_t *bd)
        ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_SYS_DPAA_FMAN
+#ifndef CONFIG_DM_ETH
        fdt_fixup_fman_ethernet(blob);
+#endif
 #endif
 
        fdt_fixup_icid(blob);