armv7: integrate cache maintenance support

[J-u-boot.git] / arch / arm / cpu / armv7 / start.S

diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 684f2d253867adc3a7b82a6a75f3b45234144917..0e698b624b6c161467b9153201ad37f9abb2e3d2 100644 (file)
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -70,6 +70,18 @@ _end_vect:
 _TEXT_BASE:
        .word   CONFIG_SYS_TEXT_BASE
 
+#ifdef CONFIG_TEGRA2
+/*
+ * Tegra2 uses 2 separate CPUs - the AVP (ARM7TDMI) and the CPU (dual A9s).
+ * U-Boot runs on the AVP first, setting things up for the CPU (PLLs,
+ * muxes, clocks, clamps, etc.). Then the AVP halts, and expects the CPU
+ * to pick up its reset vector, which points here.
+ */
+.globl _armboot_start
+_armboot_start:
+       .word _start
+#endif
+
 /*
  * These are defined in the board-specific linker script.
  */
@@ -79,6 +91,10 @@ _bss_start_ofs:
 
 .globl _bss_end_ofs
 _bss_end_ofs:
+       .word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
        .word _end - _start
 
 #ifdef CONFIG_USE_IRQ
@@ -111,7 +127,7 @@ reset:
        orr     r0, r0, #0xd3
        msr     cpsr,r0
 
-#if (CONFIG_OMAP34XX)
+#if defined(CONFIG_OMAP34XX)
        /* Copy vectors to mask ROM indirect addr */
        adr     r0, _start              @ r0 <- current position of code
        add     r0, r0, #4              @ skip reset vector
@@ -171,7 +187,6 @@ stack_setup:
        beq     clear_bss               /* skip relocation */
 #endif
        mov     r1, r6                  /* r1 <- scratch for copy_loop */
-       ldr     r2, _TEXT_BASE
        ldr     r3, _bss_start_ofs
        add     r2, r0, r3              /* r2 <- source end address         */
 
@@ -224,7 +239,6 @@ fixnext:
 clear_bss:
        ldr     r0, _bss_start_ofs
        ldr     r1, _bss_end_ofs
-       ldr     r3, _TEXT_BASE          /* Text base */
        mov     r4, r6                  /* reloc addr */
        add     r0, r0, r4
        add     r1, r1, r4
@@ -241,6 +255,14 @@ clbss_l:str        r2, [r0]                /* clear loop...                    */
  * initialization, now running from RAM.
  */
 jump_2_ram:
+/*
+ * If I-cache is enabled invalidate it
+ */
+#ifndef CONFIG_SYS_ICACHE_OFF
+       mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
+       mcr     p15, 0, r0, c7, c10, 4  @ DSB
+       mcr     p15, 0, r0, c7, c5, 4   @ ISB
+#endif
        ldr     r0, _board_init_r_ofs
        adr     r1, _start
        add     lr, r0, r1
@@ -276,6 +298,9 @@ cpu_init_crit:
        mov     r0, #0                  @ set up for MCR
        mcr     p15, 0, r0, c8, c7, 0   @ invalidate TLBs
        mcr     p15, 0, r0, c7, c5, 0   @ invalidate icache
+       mcr     p15, 0, r0, c7, c5, 6   @ invalidate BP array
+       mcr     p15, 0, r0, c7, c10, 4  @ DSB
+       mcr     p15, 0, r0, c7, c5, 4   @ ISB
 
        /*
         * disable MMU stuff and caches
@@ -284,7 +309,12 @@ cpu_init_crit:
        bic     r0, r0, #0x00002000     @ clear bits 13 (--V-)
        bic     r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
        orr     r0, r0, #0x00000002     @ set bit 1 (--A-) Align
-       orr     r0, r0, #0x00000800     @ set bit 12 (Z---) BTB
+       orr     r0, r0, #0x00000800     @ set bit 11 (Z---) BTB
+#ifdef CONFIG_SYS_ICACHE_OFF
+       bic     r0, r0, #0x00001000     @ clear bit 12 (I) I-cache
+#else
+       orr     r0, r0, #0x00001000     @ set bit 12 (I) I-cache
+#endif
        mcr     p15, 0, r0, c1, c0, 0
 
        /*