+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) Freescale Semiconductor, Inc. 2006.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
#ifndef __CONFIG_H
#define __CONFIG_H
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)
-#define CONFIG_SYS_LOWBOOT
-#endif
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */
-#define CONFIG_MPC8349 /* MPC8349 specific */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFEF00000
-#endif
-
-#define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */
-
#define CONFIG_MISC_INIT_F
-#define CONFIG_MISC_INIT_R
/*
* On-board devices
*/
-#ifdef CONFIG_MPC8349ITX
+#ifdef CONFIG_TARGET_MPC8349ITX
/* The CF card interface on the back of the board */
#define CONFIG_COMPACT_FLASH
#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
-#define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */
#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */
#endif
#define CONFIG_RTC_DS1337
#define CONFIG_SYS_I2C
-#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
/*
* Device configurations
#ifdef CONFIG_SATA_SIL3114
#define CONFIG_SYS_SATA_MAX_DEVICE 4
-#define CONFIG_LIBATA
#define CONFIG_LBA48
#endif
/*
* Support USB
*/
-#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
/* Current USB implementation supports the only USB controller,
*Flash on the Local Bus
*/
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* 127 64KB sectors + 8 8KB sectors per device */
#define CONFIG_SYS_FLASH_BANKS_LIST \
{CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000}
#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
/* Vitesse 7385 */
* BRx, ORx, LBLAWBARx, and LBLAWARx
*/
-/* Flash */
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
- | BR_PS_16 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
- | OR_UPM_XAM \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB)
/* Vitesse 7385 */
#ifdef CONFIG_VSC7385_ENET
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB \
- | OR_GPCM_CSNT \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_15 \
- | OR_GPCM_SETA \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
#endif
-/* LED */
#define CONFIG_SYS_LED_BASE 0xF9000000
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE \
- | BR_PS_8 \
- | BR_MS_GPCM \
- | BR_V)
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB \
- | OR_GPCM_CSNT \
- | OR_GPCM_ACS_DIV2 \
- | OR_GPCM_XACS \
- | OR_GPCM_SCY_9 \
- | OR_GPCM_TRLX_SET \
- | OR_GPCM_EHTR_SET \
- | OR_GPCM_EAD)
+
/* Compact Flash */
#define CONFIG_SYS_CF_BASE 0xF0000000
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE \
- | BR_PS_16 \
- | BR_MS_UPMA \
- | BR_V)
-#define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI)
-
-#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
#endif
/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONSOLE ttyS0
-#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
#endif
-#define CONFIG_PCI_66M
-#ifdef CONFIG_PCI_66M
-#define CONFIG_83XX_CLKIN 66666666 /* in Hz */
-#else
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-#endif
-
/* TSEC */
#ifdef CONFIG_TSEC_ENET
-
-#define CONFIG_MII
-#define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */
-
#define CONFIG_TSEC1
#ifdef CONFIG_TSEC1
#define CONFIG_ENV_OVERWRITE
#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */
#define CONFIG_ENV_SIZE 0x2000
#else
- #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
- #undef CONFIG_FLASH_CFI_DRIVER
- #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_SDRAM
-
-#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \
- || defined(CONFIG_USB_STORAGE)
- #define CONFIG_DOS_PARTITION
- #define CONFIG_SUPPORT_VFAT
-#endif
-
-#ifdef CONFIG_COMPACT_FLASH
- #define CONFIG_CMD_IDE
-#endif
-
-#ifdef CONFIG_SATA_SIL3114
- #define CONFIG_CMD_SATA
-#endif
-
-#if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE)
-#endif
-
-#ifdef CONFIG_PCI
- #define CONFIG_CMD_PCI
-#endif
/* Watchdog */
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
- /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
-#define CONFIG_SYS_HRCW_LOW (\
- HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
- HRCWL_DDR_TO_SCB_CLK_1X1 |\
- HRCWL_CSB_TO_CLKIN_4X1 |\
- HRCWL_VCO_1X2 |\
- HRCWL_CORE_TO_CSB_2X1)
-
-#ifdef CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0X00000100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#else
-#define CONFIG_SYS_HRCW_HIGH (\
- HRCWH_PCI_HOST |\
- HRCWH_32_BIT_PCI |\
- HRCWH_PCI1_ARBITER_ENABLE |\
- HRCWH_PCI2_ARBITER_ENABLE |\
- HRCWH_CORE_ENABLE |\
- HRCWH_FROM_0XFFF00100 |\
- HRCWH_BOOTSEQ_DISABLE |\
- HRCWH_SW_WATCHDOG_DISABLE |\
- HRCWH_ROM_LOC_LOCAL_16BIT |\
- HRCWH_TSEC1M_IN_GMII |\
- HRCWH_TSEC2M_IN_GMII)
-#endif
-
/*
* System performance
*/
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
/* USB DR as device + USB MPH as host */
#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1)
-#define CONFIG_SYS_HID0_INIT 0x00000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE
-
-#define CONFIG_SYS_HID2 HID2_HBE
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI */
-#ifdef CONFIG_PCI
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT1L 0
-#define CONFIG_SYS_IBAT1U 0
-#define CONFIG_SYS_IBAT2L 0
-#define CONFIG_SYS_IBAT2U 0
-#endif
-
-#ifdef CONFIG_MPC83XX_PCI2
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#else
-#define CONFIG_SYS_IBAT3L 0
-#define CONFIG_SYS_IBAT3U 0
-#define CONFIG_SYS_IBAT4L 0
-#define CONFIG_SYS_IBAT4U 0
-#endif
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_RW \
- | BATL_MEMCOHERENCE \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L 0
-#define CONFIG_SYS_IBAT7U 0
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#endif
#define CONFIG_NETDEV "eth0"
-#ifdef CONFIG_MPC8349ITX
-#define CONFIG_HOSTNAME "mpc8349emitx"
-#else
-#define CONFIG_HOSTNAME "mpc8349emitxgp"
-#endif
-
/* Default path and filenames */
#define CONFIG_ROOTPATH "/nfsroot/rootfs"
#define CONFIG_BOOTFILE "uImage"
/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH "u-boot.bin"
-#ifdef CONFIG_MPC8349ITX
+#ifdef CONFIG_TARGET_MPC8349ITX
#define CONFIG_FDTFILE "mpc8349emitx.dtb"
#else
#define CONFIG_FDTFILE "mpc8349emitxgp.dtb"
#endif
-#define CONFIG_BOOTARGS \
- "root=/dev/nfs rw" \
- " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
- " ip=" __stringify(CONFIG_IPADDR) ":" \
- __stringify(CONFIG_SERVERIP) ":" \
- __stringify(CONFIG_GATEWAYIP) ":" \
- __stringify(CONFIG_NETMASK) ":" \
- CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
- " console=" __stringify(CONSOLE) "," __stringify(CONFIG_BAUDRATE)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=" __stringify(CONSOLE) "\0" \
"netdev=" CONFIG_NETDEV "\0" \
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