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Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
[J-u-boot.git] / board / ti / am43xx / board.c
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index f6577769e7bff15e913eb9e891048ae0914dbaea..51fa9e04a3fb3220d42b1a035f96a060eb1d65c6 100644 (file)
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -69,6 +69,9 @@ static int read_eeprom(struct am43xx_board_id *header)
        strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
        am43xx_board_name[sizeof(header->name)] = 0;
 
        strncpy(am43xx_board_name, (char *)header->name, sizeof(header->name));
        am43xx_board_name[sizeof(header->name)] = 0;
 
+       strncpy(am43xx_board_rev, (char *)header->version, sizeof(header->version));
+       am43xx_board_rev[sizeof(header->version)] = 0;
+
        return 0;
 }
 
        return 0;
 }
 
@@ -155,12 +158,16 @@ const struct emif_regs emif_regs_lpddr2 = {
        .emif_rd_wr_lvl_rmp_ctl         = 0x0,
        .emif_rd_wr_lvl_ctl             = 0x0,
        .emif_ddr_phy_ctlr_1            = 0x0E084006,
        .emif_rd_wr_lvl_rmp_ctl         = 0x0,
        .emif_rd_wr_lvl_ctl             = 0x0,
        .emif_ddr_phy_ctlr_1            = 0x0E084006,
-       .emif_rd_wr_exec_thresh         = 0x00000405,
+       .emif_rd_wr_exec_thresh         = 0x80000405,
        .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
        .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
        .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
        .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
        .emif_ddr_ext_phy_ctrl_1        = 0x04010040,
        .emif_ddr_ext_phy_ctrl_2        = 0x00500050,
        .emif_ddr_ext_phy_ctrl_3        = 0x00500050,
        .emif_ddr_ext_phy_ctrl_4        = 0x00500050,
-       .emif_ddr_ext_phy_ctrl_5        = 0x00500050
+       .emif_ddr_ext_phy_ctrl_5        = 0x00500050,
+       .emif_prio_class_serv_map       = 0x80000001,
+       .emif_connect_id_serv_1_map     = 0x80000094,
+       .emif_connect_id_serv_2_map     = 0x00000000,
+       .emif_cos_config                        = 0x000FFFFF
 };
 
 const u32 ext_phy_ctrl_const_base_lpddr2[] = {
 };
 
 const u32 ext_phy_ctrl_const_base_lpddr2[] = {
@@ -215,7 +222,57 @@ const struct emif_regs ddr3_emif_regs_400Mhz = {
        .emif_rd_wr_lvl_rmp_win         = 0x0,
        .emif_rd_wr_lvl_rmp_ctl         = 0x0,
        .emif_rd_wr_lvl_ctl             = 0x0,
        .emif_rd_wr_lvl_rmp_win         = 0x0,
        .emif_rd_wr_lvl_rmp_ctl         = 0x0,
        .emif_rd_wr_lvl_ctl             = 0x0,
-       .emif_rd_wr_exec_thresh         = 0x00000405
+       .emif_rd_wr_exec_thresh         = 0x80000405,
+       .emif_prio_class_serv_map       = 0x80000001,
+       .emif_connect_id_serv_1_map     = 0x80000094,
+       .emif_connect_id_serv_2_map     = 0x00000000,
+       .emif_cos_config                = 0x000FFFFF
+};
+
+/* EMIF DDR3 Configurations are different for beta AM43X GP EVMs */
+const struct emif_regs ddr3_emif_regs_400Mhz_beta = {
+       .sdram_config                   = 0x638413B2,
+       .ref_ctrl                       = 0x00000C30,
+       .sdram_tim1                     = 0xEAAAD4DB,
+       .sdram_tim2                     = 0x266B7FDA,
+       .sdram_tim3                     = 0x107F8678,
+       .read_idle_ctrl                 = 0x00050000,
+       .zq_config                      = 0x50074BE4,
+       .temp_alert_config              = 0x0,
+       .emif_ddr_phy_ctlr_1            = 0x0E004008,
+       .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00000065,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
+       .emif_ddr_ext_phy_ctrl_4        = 0x000000B5,
+       .emif_ddr_ext_phy_ctrl_5        = 0x000000E5,
+       .emif_rd_wr_exec_thresh         = 0x80000405,
+       .emif_prio_class_serv_map       = 0x80000001,
+       .emif_connect_id_serv_1_map     = 0x80000094,
+       .emif_connect_id_serv_2_map     = 0x00000000,
+       .emif_cos_config                = 0x000FFFFF
+};
+
+/* EMIF DDR3 Configurations are different for production AM43X GP EVMs */
+const struct emif_regs ddr3_emif_regs_400Mhz_production = {
+       .sdram_config                   = 0x638413B2,
+       .ref_ctrl                       = 0x00000C30,
+       .sdram_tim1                     = 0xEAAAD4DB,
+       .sdram_tim2                     = 0x266B7FDA,
+       .sdram_tim3                     = 0x107F8678,
+       .read_idle_ctrl                 = 0x00050000,
+       .zq_config                      = 0x50074BE4,
+       .temp_alert_config              = 0x0,
+       .emif_ddr_phy_ctlr_1            = 0x0E004008,
+       .emif_ddr_ext_phy_ctrl_1        = 0x08020080,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00000066,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00000091,
+       .emif_ddr_ext_phy_ctrl_4        = 0x000000B9,
+       .emif_ddr_ext_phy_ctrl_5        = 0x000000E6,
+       .emif_rd_wr_exec_thresh         = 0x80000405,
+       .emif_prio_class_serv_map       = 0x80000001,
+       .emif_connect_id_serv_1_map     = 0x80000094,
+       .emif_connect_id_serv_2_map     = 0x00000000,
+       .emif_cos_config                = 0x000FFFFF
 };
 
 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
 };
 
 static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
@@ -237,7 +294,11 @@ static const struct emif_regs ddr3_sk_emif_regs_400Mhz = {
        .emif_rd_wr_lvl_rmp_win         = 0x0,
        .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
        .emif_rd_wr_lvl_rmp_win         = 0x0,
        .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
-       .emif_rd_wr_exec_thresh         = 0x00000000,
+       .emif_rd_wr_exec_thresh         = 0x80000000,
+       .emif_prio_class_serv_map       = 0x80000001,
+       .emif_connect_id_serv_1_map     = 0x80000094,
+       .emif_connect_id_serv_2_map     = 0x00000000,
+       .emif_cos_config                = 0x000FFFFF
 };
 
 const u32 ext_phy_ctrl_const_base_ddr3[] = {
 };
 
 const u32 ext_phy_ctrl_const_base_ddr3[] = {
@@ -263,6 +324,52 @@ const u32 ext_phy_ctrl_const_base_ddr3[] = {
        0x08102040
 };
 
        0x08102040
 };
 
+const u32 ext_phy_ctrl_const_base_ddr3_beta[] = {
+       0x00000000,
+       0x00000045,
+       0x00000046,
+       0x00000048,
+       0x00000047,
+       0x00000000,
+       0x0000004C,
+       0x00000070,
+       0x00000085,
+       0x000000A3,
+       0x00000000,
+       0x0000000C,
+       0x00000030,
+       0x00000045,
+       0x00000063,
+       0x00000000,
+       0x0,
+       0x0,
+       0x40000000,
+       0x08102040
+};
+
+const u32 ext_phy_ctrl_const_base_ddr3_production[] = {
+       0x00000000,
+       0x00000044,
+       0x00000044,
+       0x00000046,
+       0x00000046,
+       0x00000000,
+       0x00000059,
+       0x00000077,
+       0x00000093,
+       0x000000A8,
+       0x00000000,
+       0x00000019,
+       0x00000037,
+       0x00000053,
+       0x00000068,
+       0x00000000,
+       0x0,
+       0x0,
+       0x40000000,
+       0x08102040
+};
+
 static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
        /* first 5 are taken care by emif_regs */
        0x00700070,
 static const u32 ext_phy_ctrl_const_base_ddr3_sk[] = {
        /* first 5 are taken care by emif_regs */
        0x00700070,
@@ -310,6 +417,12 @@ void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
        if (board_is_eposevm()) {
                *regs = ext_phy_ctrl_const_base_lpddr2;
                *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
        if (board_is_eposevm()) {
                *regs = ext_phy_ctrl_const_base_lpddr2;
                *size = ARRAY_SIZE(ext_phy_ctrl_const_base_lpddr2);
+       } else if (board_is_evm_14_or_later()) {
+               *regs = ext_phy_ctrl_const_base_ddr3_production;
+               *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_production);
+       } else if (board_is_evm_12_or_later()) {
+               *regs = ext_phy_ctrl_const_base_ddr3_beta;
+               *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3_beta);
        } else if (board_is_gpevm()) {
                *regs = ext_phy_ctrl_const_base_ddr3;
                *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
        } else if (board_is_gpevm()) {
                *regs = ext_phy_ctrl_const_base_ddr3;
                *size = ARRAY_SIZE(ext_phy_ctrl_const_base_ddr3);
@@ -474,6 +587,14 @@ void sdram_init(void)
         */
        if (board_is_eposevm()) {
                config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
         */
        if (board_is_eposevm()) {
                config_ddr(0, &ioregs_lpddr2, NULL, NULL, &emif_regs_lpddr2, 0);
+       } else if (board_is_evm_14_or_later()) {
+               enable_vtt_regulator();
+               config_ddr(0, &ioregs_ddr3, NULL, NULL,
+                          &ddr3_emif_regs_400Mhz_production, 0);
+       } else if (board_is_evm_12_or_later()) {
+               enable_vtt_regulator();
+               config_ddr(0, &ioregs_ddr3, NULL, NULL,
+                          &ddr3_emif_regs_400Mhz_beta, 0);
        } else if (board_is_gpevm()) {
                enable_vtt_regulator();
                config_ddr(0, &ioregs_ddr3, NULL, NULL,
        } else if (board_is_gpevm()) {
                enable_vtt_regulator();
                config_ddr(0, &ioregs_ddr3, NULL, NULL,
@@ -500,8 +621,44 @@ int power_init_board(void)
 
 int board_init(void)
 {
 
 int board_init(void)
 {
+       struct l3f_cfg_bwlimiter *bwlimiter = (struct l3f_cfg_bwlimiter *)L3F_CFG_BWLIMITER;
+       u32 mreqprio_0, mreqprio_1, modena_init0_bw_fractional,
+           modena_init0_bw_integer, modena_init0_watermark_0;
+
        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
+       /* Clear all important bits for DSS errata that may need to be tweaked*/
+       mreqprio_0 = readl(&cdev->mreqprio_0) & MREQPRIO_0_SAB_INIT1_MASK &
+                          MREQPRIO_0_SAB_INIT0_MASK;
+
+       mreqprio_1 = readl(&cdev->mreqprio_1) & MREQPRIO_1_DSS_MASK;
+
+       modena_init0_bw_fractional = readl(&bwlimiter->modena_init0_bw_fractional) &
+                                          BW_LIMITER_BW_FRAC_MASK;
+
+       modena_init0_bw_integer = readl(&bwlimiter->modena_init0_bw_integer) &
+                                       BW_LIMITER_BW_INT_MASK;
+
+       modena_init0_watermark_0 = readl(&bwlimiter->modena_init0_watermark_0) &
+                                        BW_LIMITER_BW_WATERMARK_MASK;
+
+       /* Setting MReq Priority of the DSS*/
+       mreqprio_0 |= 0x77;
+
+       /*
+        * Set L3 Fast Configuration Register
+        * Limiting bandwith for ARM core to 700 MBPS
+        */
+       modena_init0_bw_fractional |= 0x10;
+       modena_init0_bw_integer |= 0x3;
+
+       writel(mreqprio_0, &cdev->mreqprio_0);
+       writel(mreqprio_1, &cdev->mreqprio_1);
+
+       writel(modena_init0_bw_fractional, &bwlimiter->modena_init0_bw_fractional);
+       writel(modena_init0_bw_integer, &bwlimiter->modena_init0_bw_integer);
+       writel(modena_init0_watermark_0, &bwlimiter->modena_init0_watermark_0);
+
        return 0;
 }
 
        return 0;
 }
 
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