arm: dts: stm32mp15: alignment with v5.11-rc2

[J-u-boot.git] / include / fsl_mdio.h

diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h
index 2137282df3fd97978ec6cda00530dd4487720b55..b6c02cf342de1d0964516e411aecb4a2aee463a7 100644 (file)
--- a/include/fsl_mdio.h
+++ b/include/fsl_mdio.h
@@ -1,10 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2009-2012, 2013 Freescale Semiconductor, Inc.
  *     Jun-jie Zhang <[email protected]>
  *     Mingkai Hu <[email protected]>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
+
 #ifndef __FSL_PHY_H__
 #define __FSL_PHY_H__
 
@@ -27,9 +27,9 @@ int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc);
 #define PHY_EXT_PAGE_ACCESS    0x1f
 
 /* MII Management Configuration Register */
-#define MIIMCFG_RESET_MGMT          0x80000000
-#define MIIMCFG_MGMT_CLOCK_SELECT   0x00000007
-#define MIIMCFG_INIT_VALUE         0x00000003
+#define MIIMCFG_RESET_MGMT             0x80000000
+#define MIIMCFG_MGMT_CLOCK_SELECT      0x00000007
+#define MIIMCFG_INIT_VALUE             0x00000003
 
 /* MII Management Command Register */
 #define MIIMCOM_READ_CYCLE     0x00000001
@@ -53,11 +53,16 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
                int regnum, u16 value);
 int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
                int regnum);
+int memac_mdio_reset(struct mii_dev *bus);
+
+struct fsl_pq_mdio_data {
+       u32 mdio_regs_off;
+};
 
 struct fsl_pq_mdio_info {
        struct tsec_mii_mng __iomem *regs;
        char *name;
 };
-int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info);
+int fsl_pq_mdio_init(struct bd_info *bis, struct fsl_pq_mdio_info *info);
 
 #endif /* __FSL_PHY_H__ */