doc: ti: j7200_evm: Fix OPTEE platform name

[J-u-boot.git] / arch / Kconfig.nxp

diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 5971ec5df4e6ecef371879529429d5f58d8e6a02..5a8c382ed753abe2ccd0b08ff2f4a60b0fbb651f 100644 (file)
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -1,5 +1,12 @@
+menu "Functionality shared between NXP SoCs"
+
+config FSL_TRUST_ARCH_v1
+       bool
+
 config NXP_ESBC
        bool "NXP ESBC (secure boot) functionality"
+       select FSL_TRUST_ARCH_v1 if ARCH_P3041 || ARCH_P4080 || \
+               ARCH_P5040 || ARCH_P2041
        help
          Enable Freescale Secure Boot feature. Normally selected by defconfig.
          If unsure, do not change.
@@ -10,12 +17,14 @@ menu "Chain of trust / secure boot options"
 config CHAIN_OF_TRUST
        select FSL_CAAM
        select ARCH_MISC_INIT
+       select FSL_ISBC_KEY_EXT if (ARM || FSL_CORENET) && !SYS_RAMBOOT
        select FSL_SEC_MON
        select SPL_BOARD_INIT if (ARM && SPL)
        select SPL_HASH if (ARM && SPL)
        select SHA_HW_ACCEL
        select SHA_PROG_HW_ACCEL
        select ENV_IS_NOWHERE
+       select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
        select CMD_EXT4 if ARM
        select CMD_EXT4_WRITE if ARM
        imply CMD_BLOB
@@ -36,10 +45,21 @@ config ESBC_HDR_LS
 
 config ESBC_ADDR_64BIT
        def_bool y
-       depends on ESBC_HDR_LS && FSL_LAYERSCAPE
+       depends on FSL_LAYERSCAPE
        help
          For Layerscape based platforms, ESBC image Address in Header is 64bit.
 
+config FSL_ISBC_KEY_EXT
+       bool
+       help
+         The key used for verification of next level images is picked up from
+         an Extension Table which has been verified by the ISBC (Internal
+         Secure boot Code) in boot ROM of the SoC.  The feature is only
+         applicable in case of NOR boot and is not applicable in case of
+         RAMBOOT (NAND, SD, SPI).  For Layerscape, this feature is available
+         for all device if IE Table is copied to XIP memory Also, for
+         Layerscape, ISBC doesn't verify this table.
+
 config SYS_FSL_SFP_BE
        def_bool y
        depends on PPC || FSL_LSCH2 || ARCH_LS1021A
@@ -70,7 +90,7 @@ config SPL_UBOOT_KEY_HASH
        default ""
        help
          Set the key hash for U-Boot here if public/private key pair used to
-         sign U-boot are different from the SRK hash put in the fuse.  Example
+         sign U-Boot are different from the SRK hash put in the fuse.  Example
          of a key hash is
          41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
          Otherwise leave this empty.
@@ -124,8 +144,6 @@ config KEY_REVOCATION
 
 endmenu
 
-comment "Other functionality shared between NXP SoCs"
-
 config DEEP_SLEEP
        bool "Enable SoC deep sleep feature"
        depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
@@ -226,6 +244,32 @@ config VOL_MONITOR_ISL68233_SET
 
 endif
 
+config SYS_FSL_NUM_CC_PLLS
+       int "Number of clock control PLLs"
+       depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
+       default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
+       default 6 if FSL_LSCH3 || MPC85xx
+
+config SYS_FSL_ESDHC_BE
+       bool
+
+config SYS_FSL_IFC_BE
+       bool
+
+config SYS_FSL_IFC_BANK_COUNT
+       int "Maximum banks of Integrated flash controller"
+       depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || \
+               ARCH_LS1088A || ARCH_LS1021A || ARCH_B4860 || ARCH_B4420 || \
+               ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || \
+               ARCH_T2080 || ARCH_C29X || ARCH_P1010 || ARCH_BSC9131 || \
+               ARCH_BSC9132
+       default 3 if ARCH_BSC9131 || ARCH_BSC9132
+       default 4 if ARCH_LS1043A || ARCH_LS1046A || ARCH_B4860 || \
+                       ARCH_B4420 || ARCH_P1010
+       default 8 if ARCH_LS2080A || ARCH_LS1088A || ARCH_LS1021A || \
+                       ARCH_T4240 || ARCH_T1040 || ARCH_T1042 || \
+                       ARCH_T1024 || ARCH_T2080 || ARCH_C29X
+
 config FSL_QIXIS
        bool "Enable QIXIS support"
        depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
@@ -238,3 +282,17 @@ config QIXIS_I2C_ACCESS
 config HAS_FSL_DR_USB
        def_bool y
        depends on USB_EHCI_HCD && PPC
+
+config SYS_DPAA_FMAN
+       bool
+
+config SYS_FSL_SRDS_1
+       bool
+
+config SYS_FSL_SRDS_2
+       bool
+
+config SYS_HAS_SERDES
+       bool
+
+endmenu