esdhc/usdhc: Fix PIO mode bug in fsl_esdhc driver

[J-u-boot.git] / drivers / fpga / virtex2.c

diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c
index b5a895d41a7343c783bf8bfda2d300f8e06d6dac..e092147edd1073375731eb18d253a9cf1be82a04 100644 (file)
--- a/drivers/fpga/virtex2.c
+++ b/drivers/fpga/virtex2.c
@@ -84,25 +84,25 @@
 #define CONFIG_SYS_FPGA_WAIT_CONFIG    CONFIG_SYS_HZ/5 /* 200 ms */
 #endif
 
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize);
 
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize);
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize);
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize);
 
-int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
        int ret_val = FPGA_FAIL;
 
        switch (desc->iface) {
        case slave_serial:
                PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
-               ret_val = Virtex2_ss_load (desc, buf, bsize);
+               ret_val = virtex2_ss_load(desc, buf, bsize);
                break;
 
        case slave_selectmap:
                PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
-               ret_val = Virtex2_ssm_load (desc, buf, bsize);
+               ret_val = virtex2_ssm_load(desc, buf, bsize);
                break;
 
        default:
@@ -112,19 +112,19 @@ int Virtex2_load(Xilinx_desc *desc, const void *buf, size_t bsize)
        return ret_val;
 }
 
-int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
        int ret_val = FPGA_FAIL;
 
        switch (desc->iface) {
        case slave_serial:
                PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
-               ret_val = Virtex2_ss_dump (desc, buf, bsize);
+               ret_val = virtex2_ss_dump(desc, buf, bsize);
                break;
 
        case slave_parallel:
                PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
-               ret_val = Virtex2_ssm_dump (desc, buf, bsize);
+               ret_val = virtex2_ssm_dump(desc, buf, bsize);
                break;
 
        default:
@@ -134,7 +134,7 @@ int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
        return ret_val;
 }
 
-int Virtex2_info (Xilinx_desc * desc)
+static int virtex2_info(xilinx_desc *desc)
 {
        return FPGA_SUCCESS;
 }
@@ -153,10 +153,10 @@ int Virtex2_info (Xilinx_desc * desc)
  *    INIT_B and DONE lines.  If both are high, configuration has
  *    succeeded. Congratulations!
  */
-static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
        int ret_val = FPGA_FAIL;
-       Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+       xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
 
        PRINTF ("%s:%d: Start with interface functions @ 0x%p\n",
                        __FUNCTION__, __LINE__, fn);
@@ -352,10 +352,10 @@ static int Virtex2_ssm_load(Xilinx_desc *desc, const void *buf, size_t bsize)
 /*
  * Read the FPGA configuration data
  */
-static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ssm_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
        int ret_val = FPGA_FAIL;
-       Xilinx_Virtex2_Slave_SelectMap_fns *fn = desc->iface_fns;
+       xilinx_virtex2_slave_selectmap_fns *fn = desc->iface_fns;
 
        if (fn) {
                unsigned char *data = (unsigned char *) buf;
@@ -404,16 +404,22 @@ static int Virtex2_ssm_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
        return ret_val;
 }
 
-static int Virtex2_ss_load(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_load(xilinx_desc *desc, const void *buf, size_t bsize)
 {
        printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__);
        return FPGA_FAIL;
 }
 
-static int Virtex2_ss_dump(Xilinx_desc *desc, const void *buf, size_t bsize)
+static int virtex2_ss_dump(xilinx_desc *desc, const void *buf, size_t bsize)
 {
        printf ("%s: Slave Serial Dumping is unsupported\n", __FUNCTION__);
        return FPGA_FAIL;
 }
 
 /* vim: set ts=4 tw=78: */
+
+struct xilinx_fpga_op virtex2_op = {
+       .load = virtex2_load,
+       .dump = virtex2_dump,
+       .info = virtex2_info,
+};