Merge git://git.denx.de/u-boot-arm

[J-u-boot.git] / include / configs / MPC837XEMDS.h

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 8c2af084a160c874d3c57149ab00d393cf26d9a2..51688a76bf274fc42bd31175aa9fc6eead467316 100644 (file)
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -2,20 +2,7 @@
  * Copyright (C) 2007 Freescale Semiconductor, Inc.
  * Dave Liu <[email protected]>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CONFIG_H
@@ -243,19 +230,20 @@
 
                                        /* Window base at flash base */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM     0x80000018 /* 32MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_32MB)
 
 #define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | (2 << BR_PS_SHIFT)    /* 16 bit port */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR0_PRELIM  ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+                               | BR_PS_16      /* 16 bit port */ \
+                               | BR_MS_GPCM    /* MSEL = GPCM */ \
+                               | BR_V)         /* valid */
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
                                | OR_GPCM_XACS \
                                | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX \
-                               | OR_GPCM_EHTR \
+                               | OR_GPCM_TRLX_SET \
+                               | OR_GPCM_EHTR_SET \
                                | OR_GPCM_EAD)
                                /* 0xFE000FF7 */
 
@@ -272,11 +260,22 @@
 #define CONFIG_SYS_BCSR                0xF8000000
                                        /* Access window base at BCSR base */
 #define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM     0x8000000E /* Access window size 32K */
-
-                               /* Port size=8bit, MSEL=GPCM */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_BCSR | 0x00000801)
-#define CONFIG_SYS_OR1_PRELIM  0xFFFFE9f7 /* length 32K */
+#define CONFIG_SYS_LBLAWAR1_PRELIM     (LBLAWAR_EN | LBLAWAR_32KB)
+
+#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_BCSR \
+                               | BR_PS_8 \
+                               | BR_MS_GPCM \
+                               | BR_V)
+                               /* 0xF8000801 */
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB \
+                               | OR_GPCM_XAM \
+                               | OR_GPCM_CSNT \
+                               | OR_GPCM_XACS \
+                               | OR_GPCM_SCY_15 \
+                               | OR_GPCM_TRLX_SET \
+                               | OR_GPCM_EHTR_SET \
+                               | OR_GPCM_EAD)
+                               /* 0xFFFFE9F7 */
 
 /*
  * NAND Flash on the Local Bus
@@ -286,13 +285,13 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_NAND_FSL_ELBC   1
 
-#define CONFIG_SYS_NAND_BASE   0xE0600000      /* 0xE0600000 */
+#define CONFIG_SYS_NAND_BASE   0xE0600000
 #define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_NAND_BASE \
-                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
                                | BR_PS_8               /* 8 bit port */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR3_PRELIM  (0xFFFF8000     /* length 32K */ \
+                               | BR_V)                 /* valid */
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_32KB \
                                | OR_FCM_BCTLD \
                                | OR_FCM_CST \
                                | OR_FCM_CHT \
@@ -303,7 +302,7 @@
                                /* 0xFFFF919E */
 
 #define CONFIG_SYS_LBLAWBAR3_PRELIM    CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM     0x8000000E      /* 32KB  */
+#define CONFIG_SYS_LBLAWAR3_PRELIM     (LBLAWAR_EN | LBLAWAR_32KB)
 
 /*
  * Serial Port
@@ -322,9 +321,6 @@
 
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
 
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT       1
@@ -332,14 +328,12 @@
 #define CONFIG_OF_STDOUT_VIA_ALIAS     1
 
 /* I2C */
-#define CONFIG_HARD_I2C                /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C         /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED   400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE   0x7F
-#define CONFIG_SYS_I2C_NOPROBES        {0x51} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET  0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED       400000
+#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET      0x3000
+#define CONFIG_SYS_I2C_NOPROBES                { {0, 0x51} }
 
 /*
  * Config on-board RTC
@@ -386,6 +380,7 @@
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00800000
 
 #ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
 #ifndef __ASSEMBLY__
 extern int board_pci_host_broken(void);
 #endif