i2c: Move PPC4xx I2C driver into drivers/i2c directory

[J-u-boot.git] / include / ppc4xx_enet.h

diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h
index 02084546b2f14d2a1840d50936d4e163fa70e534..3095aedc386af68754674f66ab3e174c19ade8e3 100644 (file)
--- a/include/ppc4xx_enet.h
+++ b/include/ppc4xx_enet.h
@@ -1,4 +1,6 @@
 /*----------------------------------------------------------------------------+
 /*----------------------------------------------------------------------------+

+|   This source code is dual-licensed.  You may use it under the terms of the
+|   GNU General Public License version 2, or under the license below.

 |
 |      This source code has been made available to you by IBM on an AS-IS
 |      basis.  Anyone receiving this source is licensed under IBM
 |
 |      This source code has been made available to you by IBM on an AS-IS
 |      basis.  Anyone receiving this source is licensed under IBM


@@ -117,11 +119,11 @@ typedef struct emac_4xx_hw_st {
     int                        first_init;
     int                        tx_err_index;
     int                        rx_err_index;
     int                        first_init;
     int                        tx_err_index;
     int                        rx_err_index;

-    int                        rx_slot;                        /* MAL Receive Slot */
-    int                        rx_i_index;             /* Receive Interrupt Queue Index */
-    int                        rx_u_index;             /* Receive User Queue Index */
-    int                        tx_slot;                        /* MAL Transmit Slot */
-    int                        tx_i_index;             /* Transmit Interrupt Queue Index */
+    int                        rx_slot;        /* MAL Receive Slot */
+    int                        rx_i_index;     /* Receive Interrupt Queue Index */
+    int                        rx_u_index;     /* Receive User Queue Index */
+    int                        tx_slot;        /* MAL Transmit Slot */
+    int                        tx_i_index;     /* Transmit Interrupt Queue Index */

     int                        tx_u_index;             /* Transmit User Queue Index */
     int                        rx_ready[NUM_RX_BUFF];  /* Receive Ready Queue */
     int                        tx_run[NUM_TX_BUFF];    /* Transmit Running Queue */
     int                        tx_u_index;             /* Transmit User Queue Index */
     int                        rx_ready[NUM_RX_BUFF];  /* Receive Ready Queue */
     int                        tx_run[NUM_TX_BUFF];    /* Transmit Running Queue */


@@ -153,17 +155,31 @@ typedef struct emac_4xx_hw_st {
 #define SDR0_PFC1_EM_1000      (0x00200000)
 #endif
 
 #define SDR0_PFC1_EM_1000      (0x00200000)
 #endif
 

+/*
+ * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
+ * not have a pin function control (PFC) register to otherwise determine
+ * the bridge configuration.
+ */
+#define EMAC_PHY_MODE_NONE             0
+#define EMAC_PHY_MODE_NONE_RGMII       1
+#define EMAC_PHY_MODE_RGMII_NONE       2
+#define EMAC_PHY_MODE_RGMII_RGMII      3
+#define EMAC_PHY_MODE_NONE_GMII                4
+#define EMAC_PHY_MODE_GMII_NONE                5
+#define EMAC_PHY_MODE_NONE_MII         6
+#define EMAC_PHY_MODE_MII_NONE         7
+

 /* ZMII Bridge Register addresses */
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 /* ZMII Bridge Register addresses */
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)

-#define ZMII_BASE              (CFG_PERIPHERAL_BASE + 0x0D00)
+#define ZMII0_BASE             (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)

 #else
 #else

-#define ZMII_BASE              (CFG_PERIPHERAL_BASE + 0x0780)
+#define ZMII0_BASE             (CONFIG_SYS_PERIPHERAL_BASE + 0x0780)

 #endif
 #endif

-#define ZMII_FER               (ZMII_BASE)
-#define ZMII_SSR               (ZMII_BASE + 4)
-#define ZMII_SMIISR            (ZMII_BASE + 8)
+#define ZMII0_FER              (ZMII0_BASE)
+#define ZMII0_SSR              (ZMII0_BASE + 4)
+#define ZMII0_SMIISR           (ZMII0_BASE + 8)

 
 /* ZMII FER Register Bit Definitions */
 #define ZMII_FER_DIS           (0x0)
 
 /* ZMII FER Register Bit Definitions */
 #define ZMII_FER_DIS           (0x0)


@@ -180,46 +196,50 @@ typedef struct emac_4xx_hw_st {
 
 
 /* ZMII Speed Selection Register Bit Definitions */
 
 
 /* ZMII Speed Selection Register Bit Definitions */

-#define ZMII_SSR_SCI           (0x4)
-#define ZMII_SSR_FSS           (0x2)
-#define ZMII_SSR_SP            (0x1)
-#define ZMII_SSR_RSVD16_31     (0x0000FFFF)
+#define ZMII0_SSR_SCI          (0x4)
+#define ZMII0_SSR_FSS          (0x2)
+#define ZMII0_SSR_SP           (0x1)
+#define ZMII0_SSR_RSVD16_31    (0x0000FFFF)

 
 

-#define ZMII_SSR_V(__x)                (((3 - __x) * 4) + 16)
+#define ZMII0_SSR_V(__x)               (((3 - __x) * 4) + 16)

 
 
 /* ZMII SMII Status Register Bit Definitions */
 
 
 /* ZMII SMII Status Register Bit Definitions */

-#define ZMII_SMIISR_E1         (0x80)
-#define ZMII_SMIISR_EC         (0x40)
-#define ZMII_SMIISR_EN         (0x20)
-#define ZMII_SMIISR_EJ         (0x10)
-#define ZMII_SMIISR_EL         (0x08)
-#define ZMII_SMIISR_ED         (0x04)
-#define ZMII_SMIISR_ES         (0x02)
-#define ZMII_SMIISR_EF         (0x01)
+#define ZMII0_SMIISR_E1                (0x80)
+#define ZMII0_SMIISR_EC                (0x40)
+#define ZMII0_SMIISR_EN                (0x20)
+#define ZMII0_SMIISR_EJ                (0x10)
+#define ZMII0_SMIISR_EL                (0x08)
+#define ZMII0_SMIISR_ED                (0x04)
+#define ZMII0_SMIISR_ES                (0x02)
+#define ZMII0_SMIISR_EF                (0x01)

 
 

-#define ZMII_SMIISR_V(__x)     ((3 - __x) * 8)
+#define ZMII0_SMIISR_V(__x)    ((3 - __x) * 8)

 
 /* RGMII Register Addresses */
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
 
 /* RGMII Register Addresses */
 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)

-#define RGMII_BASE             (CFG_PERIPHERAL_BASE + 0x1000)
+#define RGMII_BASE             (CONFIG_SYS_PERIPHERAL_BASE + 0x1000)

 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)

-#define RGMII_BASE             (CFG_PERIPHERAL_BASE + 0x1500)
+#define RGMII_BASE             (CONFIG_SYS_PERIPHERAL_BASE + 0x1500)

 #elif defined(CONFIG_405EX)
 #elif defined(CONFIG_405EX)

-#define RGMII_BASE             (CFG_PERIPHERAL_BASE + 0xB00)
+#define RGMII_BASE             (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)

 #else
 #else

-#define RGMII_BASE             (CFG_PERIPHERAL_BASE + 0x0790)
+#define RGMII_BASE             (CONFIG_SYS_PERIPHERAL_BASE + 0x0790)

 #endif
 #define RGMII_FER              (RGMII_BASE + 0x00)
 #define RGMII_SSR              (RGMII_BASE + 0x04)
 
 #endif
 #define RGMII_FER              (RGMII_BASE + 0x00)
 #define RGMII_SSR              (RGMII_BASE + 0x04)
 

+#if defined(CONFIG_460GT)
+#define RGMII1_BASE_OFFSET     0x100
+#endif
+

 /* RGMII Function Enable (FER) Register Bit Definitions */
 /* RGMII Function Enable (FER) Register Bit Definitions */

-/* Note: for EMAC 2 and 3 only, 440GX only */

 #define RGMII_FER_DIS          (0x00)
 #define RGMII_FER_RTBI         (0x04)
 #define RGMII_FER_RGMII                (0x05)
 #define RGMII_FER_TBI          (0x06)
 #define RGMII_FER_GMII         (0x07)
 #define RGMII_FER_DIS          (0x00)
 #define RGMII_FER_RTBI         (0x04)
 #define RGMII_FER_RGMII                (0x05)
 #define RGMII_FER_TBI          (0x06)
 #define RGMII_FER_GMII         (0x07)

+#define RGMII_FER_MII          (RGMII_FER_GMII)

 
 #define RGMII_FER_V(__x)       ((__x - 2) * 4)
 
 
 #define RGMII_FER_V(__x)       ((__x - 2) * 4)
 


@@ -242,16 +262,16 @@ typedef struct emac_4xx_hw_st {
 |  TCP/IP Acceleration Hardware (TAH) 440GX Only
 +---------------------------------------------------------------------------*/
 #if defined(CONFIG_440GX)
 |  TCP/IP Acceleration Hardware (TAH) 440GX Only
 +---------------------------------------------------------------------------*/
 #if defined(CONFIG_440GX)

-#define TAH_BASE               (CFG_PERIPHERAL_BASE + 0x0B50)
-#define TAH_REVID              (TAH_BASE + 0x0)    /* Revision ID (RO)*/
-#define TAH_MR                 (TAH_BASE + 0x10)   /* Mode Register (R/W) */
-#define TAH_SSR0               (TAH_BASE + 0x14)   /* Segment Size Reg 0 (R/W) */
-#define TAH_SSR1               (TAH_BASE + 0x18)   /* Segment Size Reg 1 (R/W) */
-#define TAH_SSR2               (TAH_BASE + 0x1C)   /* Segment Size Reg 2 (R/W) */
-#define TAH_SSR3               (TAH_BASE + 0x20)   /* Segment Size Reg 3 (R/W) */
-#define TAH_SSR4               (TAH_BASE + 0x24)   /* Segment Size Reg 4 (R/W) */
-#define TAH_SSR5               (TAH_BASE + 0x28)   /* Segment Size Reg 5 (R/W) */
-#define TAH_TSR                        (TAH_BASE + 0x2C)   /* Transmit Status Register (RO) */
+#define TAH_BASE       (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
+#define TAH_REVID      (TAH_BASE + 0x0)    /* Revision ID (RO)*/
+#define TAH_MR         (TAH_BASE + 0x10)   /* Mode Register (R/W) */
+#define TAH_SSR0       (TAH_BASE + 0x14)   /* Segment Size Reg 0 (R/W) */
+#define TAH_SSR1       (TAH_BASE + 0x18)   /* Segment Size Reg 1 (R/W) */
+#define TAH_SSR2       (TAH_BASE + 0x1C)   /* Segment Size Reg 2 (R/W) */
+#define TAH_SSR3       (TAH_BASE + 0x20)   /* Segment Size Reg 3 (R/W) */
+#define TAH_SSR4       (TAH_BASE + 0x24)   /* Segment Size Reg 4 (R/W) */
+#define TAH_SSR5       (TAH_BASE + 0x28)   /* Segment Size Reg 5 (R/W) */
+#define TAH_TSR                (TAH_BASE + 0x2C)   /* Transmit Status Register (RO) */

 
 /* TAH Revision */
 #define TAH_REV_RN_M           (0x000FFF00)        /* Revision Number */
 
 /* TAH Revision */
 #define TAH_REV_RN_M           (0x000FFF00)        /* Revision Number */


@@ -261,45 +281,45 @@ typedef struct emac_4xx_hw_st {
 #define TAH_REV_BN_V           (0)
 
 /* TAH Mode Register */
 #define TAH_REV_BN_V           (0)
 
 /* TAH Mode Register */

-#define TAH_MR_CVR             (0x80000000)        /* Checksum verification on RX */
-#define TAH_MR_SR              (0x40000000)        /* Software reset */
-#define TAH_MR_ST              (0x3F000000)        /* Send Threshold */
-#define TAH_MR_TFS             (0x00E00000)        /* Transmit FIFO size */
-#define TAH_MR_DTFP            (0x00100000)        /* Disable TX FIFO parity */
-#define TAH_MR_DIG             (0x00080000)        /* Disable interrupt generation */
-#define TAH_MR_RSVD            (0x0007FFFF)        /* Reserved */
+#define TAH_MR_CVR     (0x80000000)        /* Checksum verification on RX */
+#define TAH_MR_SR      (0x40000000)        /* Software reset */
+#define TAH_MR_ST      (0x3F000000)        /* Send Threshold */
+#define TAH_MR_TFS     (0x00E00000)        /* Transmit FIFO size */
+#define TAH_MR_DTFP    (0x00100000)        /* Disable TX FIFO parity */
+#define TAH_MR_DIG     (0x00080000)        /* Disable interrupt generation */
+#define TAH_MR_RSVD    (0x0007FFFF)        /* Reserved */

 
 

-#define TAH_MR_ST_V            (20)
-#define TAH_MR_TFS_V           (17)
+#define TAH_MR_ST_V    (20)
+#define TAH_MR_TFS_V   (17)

 
 

-#define TAH_MR_TFS_2K          (0x1)               /* Transmit FIFO size 2Kbyte */
-#define TAH_MR_TFS_4K          (0x2)               /* Transmit FIFO size 4Kbyte */
-#define TAH_MR_TFS_6K          (0x3)               /* Transmit FIFO size 6Kbyte */
-#define TAH_MR_TFS_8K          (0x4)               /* Transmit FIFO size 8Kbyte */
-#define TAH_MR_TFS_10K         (0x5)               /* Transmit FIFO size 10Kbyte (max)*/
+#define TAH_MR_TFS_2K  (0x1)       /* Transmit FIFO size 2Kbyte */
+#define TAH_MR_TFS_4K  (0x2)       /* Transmit FIFO size 4Kbyte */
+#define TAH_MR_TFS_6K  (0x3)       /* Transmit FIFO size 6Kbyte */
+#define TAH_MR_TFS_8K  (0x4)       /* Transmit FIFO size 8Kbyte */
+#define TAH_MR_TFS_10K (0x5)       /* Transmit FIFO size 10Kbyte (max)*/

 
 
 /* TAH Segment Size Registers 0:5 */
 
 
 /* TAH Segment Size Registers 0:5 */

-#define TAH_SSR_RSVD0          (0xC0000000)        /* Reserved */
-#define TAH_SSR_SS             (0x3FFE0000)        /* Segment size in multiples of 2 */
-#define TAH_SSR_RSVD1          (0x0001FFFF)        /* Reserved */
+#define TAH_SSR_RSVD0  (0xC0000000)        /* Reserved */
+#define TAH_SSR_SS     (0x3FFE0000)        /* Segment size in multiples of 2 */
+#define TAH_SSR_RSVD1  (0x0001FFFF)        /* Reserved */

 
 /* TAH Transmit Status Register */
 
 /* TAH Transmit Status Register */

-#define TAH_TSR_TFTS           (0x80000000)        /* Transmit FIFO too small */
-#define TAH_TSR_UH             (0x40000000)        /* Unrecognized header */
-#define TAH_TSR_NIPF           (0x20000000)        /* Not IPv4 */
-#define TAH_TSR_IPOP           (0x10000000)        /* IP option present */
-#define TAH_TSR_NISF           (0x08000000)        /* No IEEE SNAP format */
-#define TAH_TSR_ILTS           (0x04000000)        /* IP length too short */
-#define TAH_TSR_IPFP           (0x02000000)        /* IP fragment present */
-#define TAH_TSR_UP             (0x01000000)        /* Unsupported protocol */
-#define TAH_TSR_TFP            (0x00800000)        /* TCP flags present */
-#define TAH_TSR_SUDP           (0x00400000)        /* Segmentation for UDP */
-#define TAH_TSR_DLM            (0x00200000)        /* Data length mismatch */
-#define TAH_TSR_SIEEE          (0x00100000)        /* Segmentation for IEEE */
-#define TAH_TSR_TFPE           (0x00080000)        /* Transmit FIFO parity error */
-#define TAH_TSR_SSTS           (0x00040000)        /* Segment size too small */
-#define TAH_TSR_RSVD           (0x0003FFFF)        /* Reserved */
+#define TAH_TSR_TFTS   (0x80000000)        /* Transmit FIFO too small */
+#define TAH_TSR_UH     (0x40000000)        /* Unrecognized header */
+#define TAH_TSR_NIPF   (0x20000000)        /* Not IPv4 */
+#define TAH_TSR_IPOP   (0x10000000)        /* IP option present */
+#define TAH_TSR_NISF   (0x08000000)        /* No IEEE SNAP format */
+#define TAH_TSR_ILTS   (0x04000000)        /* IP length too short */
+#define TAH_TSR_IPFP   (0x02000000)        /* IP fragment present */
+#define TAH_TSR_UP     (0x01000000)        /* Unsupported protocol */
+#define TAH_TSR_TFP    (0x00800000)        /* TCP flags present */
+#define TAH_TSR_SUDP   (0x00400000)        /* Segmentation for UDP */
+#define TAH_TSR_DLM    (0x00200000)        /* Data length mismatch */
+#define TAH_TSR_SIEEE  (0x00100000)        /* Segmentation for IEEE */
+#define TAH_TSR_TFPE   (0x00080000)        /* Transmit FIFO parity error */
+#define TAH_TSR_SSTS   (0x00040000)        /* Segment size too small */
+#define TAH_TSR_RSVD   (0x0003FFFF)        /* Reserved */

 #endif /* CONFIG_440GX */
 
 
 #endif /* CONFIG_440GX */
 
 


@@ -308,41 +328,49 @@ typedef struct emac_4xx_hw_st {
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
     defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)

-#define EMAC_BASE              (CFG_PERIPHERAL_BASE + 0x0E00)
+#define EMAC0_BASE             (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)

 #else
 #else

-#define EMAC_BASE              (CFG_PERIPHERAL_BASE + 0x0800)
+#define EMAC0_BASE             (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)

 #endif
 #else
 #if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
 #endif
 #else
 #if defined(CONFIG_405EZ) || defined(CONFIG_405EX)

-#define EMAC_BASE              0xEF600900
+#define EMAC0_BASE             0xEF600900

 #else
 #else

-#define EMAC_BASE              0xEF600800
+#define EMAC0_BASE             0xEF600800

 #endif
 #endif
 
 #endif
 #endif
 

-#define EMAC_M0                        (EMAC_BASE)
-#define EMAC_M1                        (EMAC_BASE + 4)
-#define EMAC_TXM0              (EMAC_BASE + 8)
-#define EMAC_TXM1              (EMAC_BASE + 12)
-#define EMAC_RXM               (EMAC_BASE + 16)
-#define EMAC_ISR               (EMAC_BASE + 20)
-#define EMAC_IER               (EMAC_BASE + 24)
-#define EMAC_IAH               (EMAC_BASE + 28)
-#define EMAC_IAL               (EMAC_BASE + 32)
-#define EMAC_PAUSE_TIME_REG    (EMAC_BASE + 44)
-#define EMAC_I_FRAME_GAP_REG   (EMAC_BASE + 88)
-#define EMAC_STACR             (EMAC_BASE + 92)
-#define EMAC_TRTR              (EMAC_BASE + 96)
-#define EMAC_RX_HI_LO_WMARK    (EMAC_BASE + 100)
+#if defined(CONFIG_440EPX)
+#define EMAC1_BASE             0xEF600F00
+#define EMAC1_MR1              (EMAC1_BASE + 0x04)
+#endif
+
+#define EMAC0_MR0              (EMAC0_BASE)
+#define EMAC0_MR1              (EMAC0_BASE + 0x04)
+#define EMAC0_TMR0             (EMAC0_BASE + 0x08)
+#define EMAC0_TMR1             (EMAC0_BASE + 0x0c)
+#define EMAC0_RXM              (EMAC0_BASE + 0x10)
+#define EMAC0_ISR              (EMAC0_BASE + 0x14)
+#define EMAC0_IER              (EMAC0_BASE + 0x18)
+#define EMAC0_IAH              (EMAC0_BASE + 0x1c)
+#define EMAC0_IAL              (EMAC0_BASE + 0x20)
+#define EMAC0_PTR              (EMAC0_BASE + 0x2c)
+#define EMAC0_PAUSE_TIME_REG   EMAC0_PTR
+#define EMAC0_IPGVR            (EMAC0_BASE + 0x58)
+#define EMAC0_I_FRAME_GAP_REG  EMAC0_IPGVR
+#define EMAC0_STACR            (EMAC0_BASE + 0x5c)
+#define EMAC0_TRTR             (EMAC0_BASE + 0x60)
+#define EMAC0_RWMR             (EMAC0_BASE + 0x64)
+#define EMAC0_RX_HI_LO_WMARK   EMAC0_RWMR

 
 /* bit definitions */
 /* MODE REG 0 */
 
 /* bit definitions */
 /* MODE REG 0 */

-#define EMAC_M0_RXI            (0x80000000)
-#define EMAC_M0_TXI            (0x40000000)
-#define EMAC_M0_SRST           (0x20000000)
-#define EMAC_M0_TXE            (0x10000000)
-#define EMAC_M0_RXE            (0x08000000)
-#define EMAC_M0_WKE            (0x04000000)
+#define EMAC_MR0_RXI           (0x80000000)
+#define EMAC_MR0_TXI           (0x40000000)
+#define EMAC_MR0_SRST          (0x20000000)
+#define EMAC_MR0_TXE           (0x10000000)
+#define EMAC_MR0_RXE           (0x08000000)
+#define EMAC_MR0_WKE           (0x04000000)

 
 /* on 440GX EMAC_MR1 has a different layout! */
 #if defined(CONFIG_440GX) || \
 
 /* on 440GX EMAC_MR1 has a different layout! */
 #if defined(CONFIG_440GX) || \


@@ -351,79 +379,82 @@ typedef struct emac_4xx_hw_st {
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_405EX)
 /* MODE Reg 1 */
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_405EX)
 /* MODE Reg 1 */

-#define EMAC_M1_FDE            (0x80000000)
-#define EMAC_M1_ILE            (0x40000000)
-#define EMAC_M1_VLE            (0x20000000)
-#define EMAC_M1_EIFC           (0x10000000)
-#define EMAC_M1_APP            (0x08000000)
-#define EMAC_M1_RSVD           (0x06000000)
-#define EMAC_M1_IST            (0x01000000)
-#define EMAC_M1_MF_1000MBPS    (0x00800000)    /* 0's for 10MBPS */
-#define EMAC_M1_MF_100MBPS     (0x00400000)
-#define EMAC_M1_RFS_MASK       (0x00380000)
-#define EMAC_M1_RFS_16K                (0x00280000)
-#define EMAC_M1_RFS_8K         (0x00200000)
-#define EMAC_M1_RFS_4K         (0x00180000)
-#define EMAC_M1_RFS_2K         (0x00100000)
-#define EMAC_M1_RFS_1K         (0x00080000)
-#define EMAC_M1_TX_FIFO_MASK   (0x00070000)
-#define EMAC_M1_TX_FIFO_16K    (0x00050000)
-#define EMAC_M1_TX_FIFO_8K     (0x00040000)
-#define EMAC_M1_TX_FIFO_4K     (0x00030000)
-#define EMAC_M1_TX_FIFO_2K     (0x00020000)
-#define EMAC_M1_TX_FIFO_1K     (0x00010000)
-#define EMAC_M1_TR_MULTI       (0x00008000)    /* 0'x for single packet */
-#define EMAC_M1_MWSW           (0x00007000)
-#define EMAC_M1_JUMBO_ENABLE   (0x00000800)
-#define EMAC_M1_IPPA           (0x000007c0)
-#define EMAC_M1_OBCI_GT100     (0x00000020)
-#define EMAC_M1_OBCI_100       (0x00000018)
-#define EMAC_M1_OBCI_83                (0x00000010)
-#define EMAC_M1_OBCI_66                (0x00000008)
-#define EMAC_M1_RSVD1          (0x00000007)
+#define EMAC_MR1_FDE           (0x80000000)
+#define EMAC_MR1_ILE           (0x40000000)
+#define EMAC_MR1_VLE           (0x20000000)
+#define EMAC_MR1_EIFC          (0x10000000)
+#define EMAC_MR1_APP           (0x08000000)
+#define EMAC_MR1_RSVD          (0x06000000)
+#define EMAC_MR1_IST           (0x01000000)
+#define EMAC_MR1_MF_1000GPCS   (0x00C00000)
+#define EMAC_MR1_MF_1000MBPS   (0x00800000)    /* 0's for 10MBPS */
+#define EMAC_MR1_MF_100MBPS    (0x00400000)
+#define EMAC_MR1_RFS_MASK      (0x00380000)
+#define EMAC_MR1_RFS_16K               (0x00280000)
+#define EMAC_MR1_RFS_8K                (0x00200000)
+#define EMAC_MR1_RFS_4K                (0x00180000)
+#define EMAC_MR1_RFS_2K                (0x00100000)
+#define EMAC_MR1_RFS_1K                (0x00080000)
+#define EMAC_MR1_TX_FIFO_MASK  (0x00070000)
+#define EMAC_MR1_TX_FIFO_16K   (0x00050000)
+#define EMAC_MR1_TX_FIFO_8K    (0x00040000)
+#define EMAC_MR1_TX_FIFO_4K    (0x00030000)
+#define EMAC_MR1_TX_FIFO_2K    (0x00020000)
+#define EMAC_MR1_TX_FIFO_1K    (0x00010000)
+#define EMAC_MR1_TR_MULTI      (0x00008000)    /* 0'x for single packet */
+#define EMAC_MR1_MWSW          (0x00007000)
+#define EMAC_MR1_JUMBO_ENABLE  (0x00000800)
+#define EMAC_MR1_IPPA          (0x000007c0)
+#define EMAC_MR1_IPPA_SET(id)  (((id) & 0x1f) << 6)
+#define EMAC_MR1_IPPA_GET(id)  (((id) >> 6) & 0x1f)
+#define EMAC_MR1_OBCI_GT100    (0x00000020)
+#define EMAC_MR1_OBCI_100      (0x00000018)
+#define EMAC_MR1_OBCI_83               (0x00000010)
+#define EMAC_MR1_OBCI_66               (0x00000008)
+#define EMAC_MR1_RSVD1         (0x00000007)

 #else /* defined(CONFIG_440GX) */
 /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
 #else /* defined(CONFIG_440GX) */
 /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */

-#define EMAC_M1_FDE            0x80000000
-#define EMAC_M1_ILE            0x40000000
-#define EMAC_M1_VLE            0x20000000
-#define EMAC_M1_EIFC           0x10000000
-#define EMAC_M1_APP            0x08000000
-#define EMAC_M1_AEMI           0x02000000
-#define EMAC_M1_IST            0x01000000
-#define EMAC_M1_MF_1000MBPS    0x00800000      /* 0's for 10MBPS */
-#define EMAC_M1_MF_100MBPS     0x00400000
-#define EMAC_M1_RFS_MASK       0x00300000
-#define EMAC_M1_RFS_4K         0x00300000
-#define EMAC_M1_RFS_2K         0x00200000
-#define EMAC_M1_RFS_1K         0x00100000
-#define EMAC_M1_RFS_512                0x00000000
-#define EMAC_M1_TX_FIFO_MASK   0x000c0000
-#define EMAC_M1_TX_FIFO_2K     0x00080000
-#define EMAC_M1_TX_FIFO_1K     0x00040000
-#define EMAC_M1_TX_FIFO_512    0x00000000
-#define EMAC_M1_TR0_DEPEND     0x00010000      /* 0'x for single packet */
-#define EMAC_M1_TR0_MULTI      0x00008000
-#define EMAC_M1_TR1_DEPEND     0x00004000
-#define EMAC_M1_TR1_MULTI      0x00002000
+#define EMAC_MR1_FDE           0x80000000
+#define EMAC_MR1_ILE           0x40000000
+#define EMAC_MR1_VLE           0x20000000
+#define EMAC_MR1_EIFC          0x10000000
+#define EMAC_MR1_APP           0x08000000
+#define EMAC_MR1_AEMI          0x02000000
+#define EMAC_MR1_IST           0x01000000
+#define EMAC_MR1_MF_1000MBPS   0x00800000      /* 0's for 10MBPS */
+#define EMAC_MR1_MF_100MBPS    0x00400000
+#define EMAC_MR1_RFS_MASK      0x00300000
+#define EMAC_MR1_RFS_4K                0x00300000
+#define EMAC_MR1_RFS_2K                0x00200000
+#define EMAC_MR1_RFS_1K                0x00100000
+#define EMAC_MR1_RFS_512               0x00000000
+#define EMAC_MR1_TX_FIFO_MASK  0x000c0000
+#define EMAC_MR1_TX_FIFO_2K    0x00080000
+#define EMAC_MR1_TX_FIFO_1K    0x00040000
+#define EMAC_MR1_TX_FIFO_512   0x00000000
+#define EMAC_MR1_TR0_DEPEND    0x00010000      /* 0'x for single packet */
+#define EMAC_MR1_TR0_MULTI     0x00008000
+#define EMAC_MR1_TR1_DEPEND    0x00004000
+#define EMAC_MR1_TR1_MULTI     0x00002000

 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)

-#define EMAC_M1_JUMBO_ENABLE   0x00001000
+#define EMAC_MR1_JUMBO_ENABLE  0x00001000

 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
 #endif /* defined(CONFIG_440GX) */
 
 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
 #endif /* defined(CONFIG_440GX) */
 

-#define EMAC_MR1_FIFO_MASK     (EMAC_M1_RFS_MASK | EMAC_M1_TX_FIFO_MASK)
+#define EMAC_MR1_FIFO_MASK     (EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)

 #if defined(CONFIG_405EZ)
 /* 405EZ only supports 512 bytes fifos */
 #if defined(CONFIG_405EZ)
 /* 405EZ only supports 512 bytes fifos */

-#define EMAC_MR1_FIFO_SIZE     (EMAC_M1_RFS_512 | EMAC_M1_TX_FIFO_512)
+#define EMAC_MR1_FIFO_SIZE     (EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)

 #else
 /* Set receive fifo to 4k and tx fifo to 2k */
 #else
 /* Set receive fifo to 4k and tx fifo to 2k */

-#define EMAC_MR1_FIFO_SIZE     (EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K)
+#define EMAC_MR1_FIFO_SIZE     (EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)

 #endif
 
 /* Transmit Mode Register 0 */
 #endif
 
 /* Transmit Mode Register 0 */

-#define EMAC_TXM0_GNP0         (0x80000000)
-#define EMAC_TXM0_GNP1         (0x40000000)
-#define EMAC_TXM0_GNPD         (0x20000000)
-#define EMAC_TXM0_FC           (0x10000000)
+#define EMAC_TMR0_GNP0         (0x80000000)
+#define EMAC_TMR0_GNP1         (0x40000000)
+#define EMAC_TMR0_GNPD         (0x20000000)
+#define EMAC_TMR0_FC           (0x10000000)

 
 /* Receive Mode Register */
 #define EMAC_RMR_SP            (0x80000000)
 
 /* Receive Mode Register */
 #define EMAC_RMR_SP            (0x80000000)