Merge tag 'clk-2022.04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-clk

[J-u-boot.git] / include / sdhci.h

diff --git a/include/sdhci.h b/include/sdhci.h
index 01addb7a6036585606179a2257dca0233475b67d..c8d69f5a63f7f14ec66f13092eb12dde92679b56 100644 (file)
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -9,6 +9,8 @@
 #ifndef __SDHCI_HW_H
 #define __SDHCI_HW_H
 
+#include <linux/bitops.h>
+#include <linux/types.h>
 #include <asm/io.h>
 #include <mmc.h>
 #include <asm/gpio.h>
@@ -63,6 +65,8 @@
 #define  SDHCI_CARD_STATE_STABLE       BIT(17)
 #define  SDHCI_CARD_DETECT_PIN_LEVEL   BIT(18)
 #define  SDHCI_WRITE_PROTECT   BIT(19)
+#define  SDHCI_DATA_LVL_MASK   0x00F00000
+#define   SDHCI_DATA_0_LVL_MASK BIT(20)
 
 #define SDHCI_HOST_CONTROL     0x28
 #define  SDHCI_CTRL_LED                BIT(0)
@@ -266,10 +270,10 @@ struct sdhci_ops {
        int     (*set_ios_post)(struct sdhci_host *host);
        void    (*set_clock)(struct sdhci_host *host, u32 div);
        int (*platform_execute_tuning)(struct mmc *host, u8 opcode);
-       void (*set_delay)(struct sdhci_host *host);
+       int (*set_delay)(struct sdhci_host *host);
+       int     (*deferred_probe)(struct sdhci_host *host);
 };
 
-#if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
 #define ADMA_MAX_LEN   65532
 #ifdef CONFIG_DMA_ADDR_T_64BIT
 #define ADMA_DESC_LEN  16
@@ -300,7 +304,7 @@ struct sdhci_adma_desc {
        u32 addr_hi;
 #endif
 } __packed;
-#endif
+
 struct sdhci_host {
        const char *name;
        void *ioaddr;
@@ -321,6 +325,8 @@ struct sdhci_host {
        uint    voltages;
 
        struct mmc_config cfg;
+       void *align_buffer;
+       bool force_align_buffer;
        dma_addr_t start_addr;
        int flags;
 #define USE_SDMA       (0x1 << 0)
@@ -330,7 +336,6 @@ struct sdhci_host {
        dma_addr_t adma_addr;
 #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
        struct sdhci_adma_desc *adma_desc_table;
-       uint desc_slot;
 #endif
 };
 
@@ -437,10 +442,10 @@ static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
  * ...
  *
  * Inside U_BOOT_DRIVER():
- *     .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
+ *     .plat_auto      = sizeof(struct msm_sdhc_plat),
  *
  * To access platform data:
- *     struct msm_sdhc_plat *plat = dev_get_platdata(dev);
+ *     struct msm_sdhc_plat *plat = dev_get_plat(dev);
  *
  * See msm_sdhci.c for an example.
  *
@@ -465,7 +470,7 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
  * @cfg:       Empty configuration structure (generally &plat->cfg). This is
  *             normally all zeroes at this point. The only purpose of passing
  *             this in is to set mmc->cfg to it.
- * @return 0 if OK, -ve if the block device could not be created
+ * Return: 0 if OK, -ve if the block device could not be created
  */
 int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
 #else
@@ -478,7 +483,7 @@ int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg);
  * @host:      SDHCI host structure
  * @f_max:     Maximum supported clock frequency in HZ (0 for default)
  * @f_min:     Minimum supported clock frequency in HZ (0 for default)
- * @return 0 if OK, -ve on error
+ * Return: 0 if OK, -ve on error
  */
 int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min);
 #endif /* !CONFIG_BLK */
@@ -488,8 +493,22 @@ void sdhci_set_uhs_timing(struct sdhci_host *host);
 /* Export the operations to drivers */
 int sdhci_probe(struct udevice *dev);
 int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
+
+/**
+ * sdhci_set_control_reg - Set control registers
+ *
+ * This is used set up control registers for voltage level and UHS speed
+ * mode.
+ *
+ * @host: SDHCI host structure
+ */
+void sdhci_set_control_reg(struct sdhci_host *host);
 extern const struct dm_mmc_ops sdhci_ops;
 #else
 #endif
 
+struct sdhci_adma_desc *sdhci_adma_init(void);
+void sdhci_prepare_adma_table(struct sdhci_adma_desc *table,
+                             struct mmc_data *data, dma_addr_t addr);
+
 #endif /* __SDHCI_HW_H */