command: Remove the cmd_tbl_t typedef

[J-u-boot.git] / drivers / mmc / dw_mmc.c

diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 7544b84ab614cbd525ad5a9dc1100e4967886455..6290b7fb5be133c068fa8561f516b47dc61fd440 100644 (file)
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -7,11 +7,15 @@
 
 #include <bouncebuf.h>
 #include <common.h>
+#include <cpu_func.h>
 #include <errno.h>
 #include <malloc.h>
 #include <memalign.h>
 #include <mmc.h>
 #include <dwmmc.h>
+#include <wait_bit.h>
+#include <asm/cache.h>
+#include <power/regulator.h>
 
 #define PAGE_SIZE 4096
 
@@ -55,6 +59,9 @@ static void dwmci_prepare_data(struct dwmci_host *host,
 
        dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
 
+       /* Clear IDMAC interrupt */
+       dwmci_writel(host, DWMCI_IDSTS, 0xFFFFFFFF);
+
        data_start = (ulong)cur_idmac;
        dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
 
@@ -70,15 +77,15 @@ static void dwmci_prepare_data(struct dwmci_host *host,
                dwmci_set_idma_desc(cur_idmac, flags, cnt,
                                    (ulong)bounce_buffer + (i * PAGE_SIZE));
 
+               cur_idmac++;
                if (blk_cnt <= 8)
                        break;
                blk_cnt -= 8;
-               cur_idmac++;
                i++;
        } while(1);
 
        data_end = (ulong)cur_idmac;
-       flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
+       flush_dcache_range(data_start, roundup(data_end, ARCH_DMA_MINALIGN));
 
        ctrl = dwmci_readl(host, DWMCI_CTRL);
        ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
@@ -110,22 +117,41 @@ static int dwmci_fifo_ready(struct dwmci_host *host, u32 bit, u32 *len)
        return 0;
 }
 
+static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size)
+{
+       unsigned int timeout;
+
+       timeout = size * 8;     /* counting in bits */
+       timeout *= 10;          /* wait 10 times as long */
+       timeout /= mmc->clock;
+       timeout /= mmc->bus_width;
+       timeout /= mmc->ddr_mode ? 2 : 1;
+       timeout *= 1000;        /* counting in msec */
+       timeout = (timeout < 1000) ? 1000 : timeout;
+
+       return timeout;
+}
+
 static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
 {
+       struct mmc *mmc = host->mmc;
        int ret = 0;
-       u32 timeout = 240000;
-       u32 mask, size, i, len = 0;
+       u32 timeout, mask, size, i, len = 0;
        u32 *buf = NULL;
        ulong start = get_timer(0);
        u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
                            RX_WMARK_SHIFT) + 1) * 2;
 
-       size = data->blocksize * data->blocks / 4;
+       size = data->blocksize * data->blocks;
        if (data->flags == MMC_DATA_READ)
                buf = (unsigned int *)data->dest;
        else
                buf = (unsigned int *)data->src;
 
+       timeout = dwmci_get_timeout(mmc, size);
+
+       size /= 4;
+
        for (;;) {
                mask = dwmci_readl(host, DWMCI_RINTSTS);
                /* Error during data transfer. */
@@ -248,14 +274,20 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
                        dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
                } else {
                        if (data->flags == MMC_DATA_READ) {
-                               bounce_buffer_start(&bbstate, (void*)data->dest,
+                               ret = bounce_buffer_start(&bbstate,
+                                               (void*)data->dest,
                                                data->blocksize *
                                                data->blocks, GEN_BB_WRITE);
                        } else {
-                               bounce_buffer_start(&bbstate, (void*)data->src,
+                               ret = bounce_buffer_start(&bbstate,
+                                               (void*)data->src,
                                                data->blocksize *
                                                data->blocks, GEN_BB_READ);
                        }
+
+                       if (ret)
+                               return ret;
+
                        dwmci_prepare_data(host, data, cur_idmac,
                                           bbstate.bounce_buffer);
                }
@@ -340,6 +372,18 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 
                /* only dma mode need it */
                if (!host->fifo_mode) {
+                       if (data->flags == MMC_DATA_READ)
+                               mask = DWMCI_IDINTEN_RI;
+                       else
+                               mask = DWMCI_IDINTEN_TI;
+                       ret = wait_for_bit_le32(host->ioaddr + DWMCI_IDSTS,
+                                               mask, true, 1000, false);
+                       if (ret)
+                               debug("%s: DWMCI_IDINTEN mask 0x%x timeout.\n",
+                                     __func__, mask);
+                       /* clear interrupts */
+                       dwmci_writel(host, DWMCI_IDSTS, DWMCI_IDINTEN_MASK);
+
                        ctrl = dwmci_readl(host, DWMCI_CTRL);
                        ctrl &= ~(DWMCI_DMA_EN);
                        dwmci_writel(host, DWMCI_CTRL, ctrl);
@@ -453,6 +497,21 @@ static int dwmci_set_ios(struct mmc *mmc)
        if (host->clksel)
                host->clksel(host);
 
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+       if (mmc->vqmmc_supply) {
+               int ret;
+
+               if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
+                       regulator_set_value(mmc->vqmmc_supply, 1800000);
+               else
+                       regulator_set_value(mmc->vqmmc_supply, 3300000);
+
+               ret = regulator_set_enable_if_allowed(mmc->vqmmc_supply, true);
+               if (ret)
+                       return ret;
+       }
+#endif
+
        return 0;
 }
 
@@ -494,6 +553,9 @@ static int dwmci_init(struct mmc *mmc)
        dwmci_writel(host, DWMCI_CLKENA, 0);
        dwmci_writel(host, DWMCI_CLKSRC, 0);
 
+       if (!host->fifo_mode)
+               dwmci_writel(host, DWMCI_IDINTEN, DWMCI_IDINTEN_MASK);
+
        return 0;
 }