*/
#include <common.h>
+#include <cpu_func.h>
#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <net.h>
+#include <linux/delay.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/sata.h>
#include <asm/mach-imx/video.h>
+#include <cpu.h>
#include <dm/platform_data/serial_mxc.h>
-#include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
#include <imx_thermal.h>
-#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
+#include <cpu.h>
#include "../common/tdx-cfg-block.h"
#ifdef CONFIG_TDX_CMD_IMX_MFGR
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
- PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
- PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define USDHC_EMMC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
+ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
+ PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
-#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
/* Colibri MMC */
iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* eMMC */
iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+ MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+ MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+ MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+ MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+ MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+ MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+ MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+ MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
+ MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
-
-iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
-
-static void setup_iomux_enet(void)
-{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
-}
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
/* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
iomux_v3_cfg_t const gpio_pads[] = {
* UARTs are used in DTE mode, switch the mode on all UARTs before
* any pinmuxing connects a (DCE) output to a transceiver output.
*/
+#define UCR3 0x88 /* FIFO Control Register */
+#define UCR3_RI BIT(8) /* RIDELT DTE mode */
+#define UCR3_DCD BIT(9) /* DCDDELT DTE mode */
#define UFCR 0x90 /* FIFO Control Register */
-#define UFCR_DCEDTE (1<<6) /* DCE=0 */
+#define UFCR_DCEDTE BIT(6) /* DCE=0 */
static void setup_dtemode_uart(void)
{
setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
+
+ clrbits_le32((u32 *)(UART1_BASE + UCR3), UCR3_DCD | UCR3_RI);
+ clrbits_le32((u32 *)(UART2_BASE + UCR3), UCR3_DCD | UCR3_RI);
+ clrbits_le32((u32 *)(UART3_BASE + UCR3), UCR3_DCD | UCR3_RI);
}
static void setup_iomux_uart(void)
}
#endif
-#if defined(CONFIG_FSL_ESDHC) && defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD)
/* use the following sequence: eMMC, MMC */
struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
{USDHC3_BASE_ADDR},
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
int board_phy_config(struct phy_device *phydev)
{
return 0;
}
-int board_eth_init(bd_t *bis)
+int setup_fec(void)
{
- struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- uint32_t base = IMX_FEC_BASE;
- struct mii_dev *bus = NULL;
- struct phy_device *phydev = NULL;
int ret;
+ struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* provide the PHY clock from the i.MX 6 */
ret = enable_fec_anatop_clock(0, ENET_50MHZ);
if (ret)
return ret;
- /* set gpr1[ENET_CLK_SEL] */
setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
- setup_iomux_enet();
-
-#ifdef CONFIG_FEC_MXC
- bus = fec_get_miibus(base, -1);
- if (!bus)
- return 0;
-
- /* scan PHY 1..7 */
- phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
- if (!phydev) {
- free(bus);
- puts("no PHY found\n");
- return 0;
- }
-
- phy_reset(phydev);
- printf("using PHY at %d\n", phydev->addr);
- ret = fec_probe(bis, -1, base, bus, phydev);
- if (ret) {
- printf("FEC MXC: %s:failed\n", __func__);
- free(phydev);
- free(bus);
- }
-#endif /* CONFIG_FEC_MXC */
-
return 0;
}
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
+#if defined(CONFIG_FEC_MXC)
+ setup_fec();
+#endif
#if defined(CONFIG_VIDEO_IPUV3)
setup_display();
#endif
env_set("board_rev", env_str);
#endif
+#ifdef CONFIG_CMD_USB_SDP
+ if (is_boot_from_usb()) {
+ printf("Serial Downloader recovery mode, using sdp command\n");
+ env_set("bootdelay", "0");
+ env_set("bootcmd", "sdp 0");
+ }
+#endif /* CONFIG_CMD_USB_SDP */
+
return 0;
}
#endif /* CONFIG_BOARD_LATE_INIT */
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
- return ft_common_board_setup(blob, bd);
+ u32 cma_size;
+
+ ft_common_board_setup(blob, bd);
+
+ cma_size = env_get_ulong("cma-size", 10, 320 * 1024 * 1024);
+ cma_size = min((u32)(gd->ram_size >> 1), cma_size);
+
+ fdt_setprop_u32(blob,
+ fdt_path_offset(blob, "/reserved-memory/linux,cma"),
+ "size",
+ cma_size);
+ return 0;
}
#endif
case TEMP_AUTOMOTIVE:
default:
if (is_cpu_type(MXC_CPU_MX6DL)) {
+ puts("Industrial temperature grade DDR3 timings, 64bit bus width.\n");
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else {
puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
udelay(100);
}
+static iomux_v3_cfg_t const gpio_reset_pad[] = {
+ MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL) |
+ MUX_MODE_SION
+#define GPIO_NRESET IMX_GPIO_NR(6, 27)
+};
+
+#define IMX_RESET_CAUSE_POR 0x00011
+static void nreset_out(void)
+{
+ int reset_cause = get_imx_reset_cause();
+
+ if (reset_cause != IMX_RESET_CAUSE_POR) {
+ imx_iomux_v3_setup_multiple_pads(gpio_reset_pad,
+ ARRAY_SIZE(gpio_reset_pad));
+ gpio_direction_output(GPIO_NRESET, 1);
+ udelay(100);
+ gpio_direction_output(GPIO_NRESET, 0);
+ }
+}
+
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
+ /* Assert nReset_Out */
+ nreset_out();
+
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
projects / J-u-boot.git / blobdiff