* the whole RAM.
*/
-#ifdef CONFIG_POST
-
#include <post.h>
#include <watchdog.h>
-#if CONFIG_POST & CFG_POST_MEMORY
+#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
DECLARE_GLOBAL_DATA_PTR;
*
* For other processors, let the compiler generate the best code it can.
*/
-static void move64(unsigned long long *src, unsigned long long *dest)
+static void move64(const unsigned long long *src, unsigned long long *dest)
{
#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X)
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
static int memory_post_dataline(unsigned long long * pmem)
{
unsigned long long temp64 = 0;
- int num_patterns = sizeof(pattern)/ sizeof(pattern[0]);
+ int num_patterns = ARRAY_SIZE(pattern);
int i;
unsigned int hi, lo, pathi, patlo;
int ret = 0;
for ( i = 0; i < num_patterns; i++) {
- move64((unsigned long long *)&(pattern[i]), pmem++);
+ move64(&(pattern[i]), pmem++);
/*
* Put a different pattern on the data lines: otherwise they
* may float long enough to read back what we wrote.
*/
- move64((unsigned long long *)&otherpattern, pmem--);
+ move64(&otherpattern, pmem--);
move64(pmem, &temp64);
#ifdef INJECT_DATA_ERRORS
#endif
if(readback == *testaddr) {
post_log ("Memory (address line) error at %08x<->%08x, "
- "XOR value %08x !\n",
+ "XOR value %08x !\n",
testaddr, target, xor);
ret = -1;
}
return ret;
}
-int memory_post_test (int flags)
+__attribute__((weak))
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
- int ret = 0;
bd_t *bd = gd->bd;
- unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
- 256 << 20 : bd->bi_memsize) - (1 << 20);
+ *vstart = CONFIG_SYS_SDRAM_BASE;
+ *size = (bd->bi_memsize >= 256 << 20 ?
+ 256 << 20 : bd->bi_memsize) - (1 << 20);
+
+ /* Limit area to be tested with the board info struct */
+ if ((*vstart) + (*size) > (ulong)bd)
+ *size = (ulong)bd - *vstart;
+
+ return 0;
+}
+__attribute__((weak))
+int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ return 1;
+}
- if (flags & POST_SLOWTEST) {
- ret = memory_post_tests (CFG_SDRAM_BASE, memsize);
- } else { /* POST_NORMAL */
+__attribute__((weak))
+int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ return 0;
+}
- unsigned long i;
+__attribute__((weak))
+void arch_memory_failure_handle(void)
+{
+ return;
+}
- for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
- if (ret == 0)
- ret = memory_post_tests (i << 20, 0x800);
- if (ret == 0)
- ret = memory_post_tests ((i << 20) + 0xff800, 0x800);
+int memory_post_test(int flags)
+{
+ int ret = 0;
+ phys_addr_t phys_offset = 0;
+ u32 memsize, vstart;
+
+ arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
+
+ do {
+ if (flags & POST_SLOWTEST) {
+ ret = memory_post_tests(vstart, memsize);
+ } else { /* POST_NORMAL */
+ unsigned long i;
+ for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
+ if (ret == 0)
+ ret = memory_post_tests(i << 20, 0x800);
+ if (ret == 0)
+ ret = memory_post_tests(
+ (i << 20) + 0xff800, 0x800);
+ }
}
- }
+ } while (!ret &&
+ !arch_memory_test_advance(&vstart, &memsize, &phys_offset));
+
+ arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
+ if (ret)
+ arch_memory_failure_handle();
return ret;
}
-#endif /* CONFIG_POST & CFG_POST_MEMORY */
-#endif /* CONFIG_POST */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */