Prepare v2025.01-rc1

[J-u-boot.git] / doc / README.fsl-ddr

diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index 10e63f3be1d3bd4505727e5561aee45932035c16..f44bb2aa25d4865157e9eb12edc67523003ce9af 100644 (file)
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -56,8 +56,8 @@ Table of 2-way interleaving modes supported in cpu/8xxx/ddr/
 The ways to configure the ddr interleaving mode
 ==============================================
 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting
-   under "CONFIG_EXTRA_ENV_SETTINGS", like:
-       #define CONFIG_EXTRA_ENV_SETTINGS                               \
+   under "CFG_EXTRA_ENV_SETTINGS", like:
+       #define CFG_EXTRA_ENV_SETTINGS                          \
         "hwconfig=fsl_ddr:ctlr_intlv=bank"                     \
         ......