Merge patch series "Add TI K3 PCIe Controller support for J7200"

[J-u-boot.git] / drivers / net / rtl8169.c

diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c
index 2276a465e7878c4dbfd1ccf7ccd9c76103e08b2f..edcae88a3fc5be371da5e4fc91066a97685e82e4 100644 (file)
--- a/drivers/net/rtl8169.c
+++ b/drivers/net/rtl8169.c
@@ -39,7 +39,6 @@
  * 26 August 2006 Mihai Georgian <[email protected]>
  * Modified to use le32_to_cpu and cpu_to_le32 properly
  */
-#include <common.h>
 #include <cpu_func.h>
 #include <dm.h>
 #include <errno.h>
@@ -51,6 +50,7 @@
 #include <asm/io.h>
 #include <pci.h>
 #include <linux/delay.h>
+#include <linux/printk.h>
 
 #undef DEBUG_RTL8169
 #undef DEBUG_RTL8169_TX
@@ -96,12 +96,12 @@ static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
 #define TX_TIMEOUT  (6*HZ)
 
 /* write/read MMIO register. Notice: {read,write}[wl] do the necessary swapping */
-#define RTL_W8(reg, val8)      writeb((val8), ioaddr + (reg))
-#define RTL_W16(reg, val16)    writew((val16), ioaddr + (reg))
-#define RTL_W32(reg, val32)    writel((val32), ioaddr + (reg))
-#define RTL_R8(reg)            readb(ioaddr + (reg))
-#define RTL_R16(reg)           readw(ioaddr + (reg))
-#define RTL_R32(reg)           readl(ioaddr + (reg))
+#define RTL_W8(reg, val8)      writeb((val8), (void *)(ioaddr + (reg)))
+#define RTL_W16(reg, val16)    writew((val16), (void *)(ioaddr + (reg)))
+#define RTL_W32(reg, val32)    writel((val32), (void *)(ioaddr + (reg)))
+#define RTL_R8(reg)            readb((void *)(ioaddr + (reg)))
+#define RTL_R16(reg)           readw((void *)(ioaddr + (reg)))
+#define RTL_R32(reg)           readl((void *)(ioaddr + (reg)))
 
 #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)(unsigned long)dev->priv, \
        (pci_addr_t)(unsigned long)a)
@@ -311,10 +311,12 @@ static unsigned char rxdata[RX_BUF_LEN];
  *
  * This can be fixed by defining CONFIG_SYS_NONCACHED_MEMORY which will cause
  * the driver to allocate descriptors from a pool of non-cached memory.
+ *
+ * Hardware maintain D-cache coherency in RISC-V architecture.
  */
 #if RTL8169_DESC_SIZE < ARCH_DMA_MINALIGN
 #if !defined(CONFIG_SYS_NONCACHED_MEMORY) && \
-       !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86)
+       !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_X86) && !defined(CONFIG_RISCV)
 #warning cache-line size is larger than descriptor size
 #endif
 #endif
@@ -351,10 +353,11 @@ static const unsigned int rtl8169_rx_config =
     (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 
 static struct pci_device_id supported[] = {
+       { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) },
+       { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161) },
        { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167) },
        { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168) },
        { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169) },
-       { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125) },
        {}
 };
 
@@ -733,7 +736,6 @@ static void rtl8169_hw_start(struct udevice *dev)
        RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
                                (InterFrameGap << TxInterFrameGapShift));
 
-
        tpc->cur_rx = 0;
 
        RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
@@ -1028,7 +1030,6 @@ static int rtl_init(unsigned long dev_ioaddr, const char *name,
 #endif
        }
 
-
        tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
        if (!tpc->RxDescArray)
                return -ENOMEM;
@@ -1049,8 +1050,9 @@ static int rtl8169_eth_probe(struct udevice *dev)
        int ret;
 
        switch (pplat->device) {
-       case 0x8168:
        case 0x8125:
+       case 0x8161:
+       case 0x8168:
                region = 2;
                break;
        default: