#include <common.h>
#include <malloc.h>
-#include <asm/fec.h>
-#include <asm/immap.h>
-
#include <command.h>
-#include <config.h>
#include <net.h>
+#include <netdev.h>
#include <miiphy.h>
-#ifdef CONFIG_MCFFEC
+#include <asm/fec.h>
+#include <asm/immap.h>
+
#undef ET_DEBUG
#undef MII_DEBUG
DECLARE_GLOBAL_DATA_PTR;
-#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
-
struct fec_info_s fec_info[] = {
-#ifdef CFG_FEC0_IOBASE
+#ifdef CONFIG_SYS_FEC0_IOBASE
{
0, /* index */
- CFG_FEC0_IOBASE, /* io base */
- CFG_FEC0_PINMUX, /* gpio pin muxing */
- CFG_FEC0_MIIBASE, /* mii base */
+ CONFIG_SYS_FEC0_IOBASE, /* io base */
+ CONFIG_SYS_FEC0_PINMUX, /* gpio pin muxing */
+ CONFIG_SYS_FEC0_MIIBASE, /* mii base */
-1, /* phy_addr */
0, /* duplex and speed */
0, /* phy name */
0, /* tx Index */
0, /* tx buffer */
0, /* initialized flag */
+ (struct fec_info_s *)-1,
},
#endif
-#ifdef CFG_FEC1_IOBASE
+#ifdef CONFIG_SYS_FEC1_IOBASE
{
1, /* index */
- CFG_FEC1_IOBASE, /* io base */
- CFG_FEC1_PINMUX, /* gpio pin muxing */
- CFG_FEC1_MIIBASE, /* mii base */
+ CONFIG_SYS_FEC1_IOBASE, /* io base */
+ CONFIG_SYS_FEC1_PINMUX, /* gpio pin muxing */
+ CONFIG_SYS_FEC1_MIIBASE, /* mii base */
-1, /* phy_addr */
0, /* duplex and speed */
0, /* phy name */
0, /* phy name init */
+#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
+ (cbd_t *)DBUF_LENGTH, /* RX BD */
+#else
0, /* RX BD */
+#endif
0, /* TX BD */
0, /* rx Index */
0, /* tx Index */
0, /* tx buffer */
0, /* initialized flag */
+ (struct fec_info_s *)-1,
}
#endif
};
void fec_halt(struct eth_device *dev);
void fec_reset(struct eth_device *dev);
-extern int fecpin_setclear(struct eth_device *dev, int setclear);
-
-#ifdef CFG_DISCOVER_PHY
-extern void mii_init(void);
-extern uint mii_send(uint mii_cmd);
-extern int mii_discover_phy(struct eth_device *dev);
-extern int mcffec_miiphy_read(char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value);
-extern int mcffec_miiphy_write(char *devname, unsigned char addr,
- unsigned char reg, unsigned short value);
-#endif
-
void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd)
{
if ((dup_spd >> 16) == FULL) {
}
if ((dup_spd & 0xFFFF) == _100BASET) {
+#ifdef CONFIG_MCF5445x
+ fecp->rcr &= ~0x200; /* disabled 10T base */
+#endif
#ifdef MII_DEBUG
printf("100Mbps\n");
#endif
bd->bi_ethspeed = 100;
} else {
+#ifdef CONFIG_MCF5445x
+ fecp->rcr |= 0x200; /* enabled 10T base */
+#endif
#ifdef MII_DEBUG
printf("10Mbps\n");
#endif
int j, rc;
u16 phyStatus;
- miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus);
+ miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phyStatus);
/* section 16.9.23.3
* Wait for ready
/* Activate transmit Buffer Descriptor polling */
fecp->tdar = 0x01000000; /* Descriptor polling active */
-#ifdef CFG_UNIFY_CACHE
+#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
+ /*
+ * FEC unable to initial transmit data packet.
+ * A nop will ensure the descriptor polling active completed.
+ * CF Internal RAM has shorter cycle access than DRAM. If use
+ * DRAM as Buffer descriptor and data, a nop is a must.
+ * Affect only V2 and V3.
+ */
+ __asm__ ("nop");
+
+#endif
+
+#ifdef CONFIG_SYS_UNIFY_CACHE
icache_invalid();
#endif
+
j = 0;
while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
(j < MCFFEC_TOUT_LOOP)) {
int length;
for (;;) {
-#ifdef CFG_UNIFY_CACHE
- icache_invalid();
+#ifndef CONFIG_SYS_FEC_BUF_USE_SRAM
+#endif
+#ifdef CONFIG_SYS_UNIFY_CACHE
+ icache_invalid();
#endif
/* section 16.9.23.2 */
if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
struct fec_info_s *info = dev->priv;
volatile fec_t *fecp = (fec_t *) (info->iobase);
int i;
- u8 *ea = NULL;
+ uchar ea[6];
fecpin_setclear(dev, 1);
fec_reset(dev);
-#if (CONFIG_COMMANDS & CFG_CMD_MII) || defined (CONFIG_MII) || \
- defined (CFG_DISCOVER_PHY)
+#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
+ defined (CONFIG_SYS_DISCOVER_PHY)
mii_init();
setFecDuplexSpeed(fecp, bd, info->dup_spd);
#else
-#ifndef CFG_DISCOVER_PHY
+#ifndef CONFIG_SYS_DISCOVER_PHY
setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED);
-#endif /* ifndef CFG_DISCOVER_PHY */
-#endif /* CFG_CMD_MII || CONFIG_MII */
+#endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
+#endif /* CONFIG_CMD_MII || CONFIG_MII */
/* We use strictly polling mode only */
fecp->eimr = 0;
fecp->eir = 0xffffffff;
/* Set station address */
- if ((u32) fecp == CFG_FEC0_IOBASE) {
- ea = &bd->bi_enetaddr[0];
+ if ((u32) fecp == CONFIG_SYS_FEC0_IOBASE) {
+#ifdef CONFIG_SYS_FEC1_IOBASE
+ volatile fec_t *fecp1 = (fec_t *) (CONFIG_SYS_FEC1_IOBASE);
+ eth_getenv_enetaddr("eth1addr", ea);
+ fecp1->palr =
+ (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
+ fecp1->paur = (ea[4] << 24) | (ea[5] << 16);
+#endif
+ eth_getenv_enetaddr("ethaddr", ea);
+ fecp->palr =
+ (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
+ fecp->paur = (ea[4] << 24) | (ea[5] << 16);
} else {
-#ifdef CFG_FEC1_IOBASE
- ea = &bd->bi_enet1addr[0];
+#ifdef CONFIG_SYS_FEC0_IOBASE
+ volatile fec_t *fecp0 = (fec_t *) (CONFIG_SYS_FEC0_IOBASE);
+ eth_getenv_enetaddr("ethaddr", ea);
+ fecp0->palr =
+ (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
+ fecp0->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
- }
-
- fecp->palr = (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
- fecp->paur = (ea[4] << 24) | (ea[5] << 16);
-#ifdef ET_DEBUG
- printf("Eth Addrs: %02x:%02x:%02x:%02x:%02x:%02x\n",
- ea[0], ea[1], ea[2], ea[3], ea[4], ea[5]);
+#ifdef CONFIG_SYS_FEC1_IOBASE
+ eth_getenv_enetaddr("eth1addr", ea);
+ fecp->palr =
+ (ea[0] << 24) | (ea[1] << 16) | (ea[2] << 8) | (ea[3]);
+ fecp->paur = (ea[4] << 24) | (ea[5] << 16);
#endif
+ }
/* Clear unicast address hash table */
fecp->iaur = 0;
{
struct eth_device *dev;
int i;
+#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
+ u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
+#endif
for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) {
dev =
- (struct eth_device *)memalign(CFG_CACHELINE_SIZE,
+ (struct eth_device *)memalign(CONFIG_SYS_CACHELINE_SIZE,
sizeof *dev);
if (dev == NULL)
hang();
dev->recv = fec_recv;
/* setup Receive and Transmit buffer descriptor */
+#ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
+ fec_info[i].rxbd = (cbd_t *)((u32)fec_info[i].rxbd + tmp);
+ tmp = (u32)fec_info[i].rxbd;
+ fec_info[i].txbd =
+ (cbd_t *)((u32)fec_info[i].txbd + tmp +
+ (PKTBUFSRX * sizeof(cbd_t)));
+ tmp = (u32)fec_info[i].txbd;
+ fec_info[i].txbuf =
+ (char *)((u32)fec_info[i].txbuf + tmp +
+ (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
+ tmp = (u32)fec_info[i].txbuf;
+#else
fec_info[i].rxbd =
- (cbd_t *) memalign(CFG_CACHELINE_SIZE,
+ (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
(PKTBUFSRX * sizeof(cbd_t)));
fec_info[i].txbd =
- (cbd_t *) memalign(CFG_CACHELINE_SIZE,
+ (cbd_t *) memalign(CONFIG_SYS_CACHELINE_SIZE,
(TX_BUF_CNT * sizeof(cbd_t)));
fec_info[i].txbuf =
- (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH);
+ (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
+#endif
+
#ifdef ET_DEBUG
printf("rxbd %x txbd %x\n",
(int)fec_info[i].rxbd, (int)fec_info[i].txbd);
#endif
- fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32);
+ fec_info[i].phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
eth_register(dev);
-#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name,
mcffec_miiphy_read, mcffec_miiphy_write);
#endif
+ if (i > 0)
+ fec_info[i - 1].next = &fec_info[i];
}
+ fec_info[i - 1].next = &fec_info[0];
/* default speed */
bis->bi_ethspeed = 10;
- return 1;
+ return 0;
}
-
-#endif /* CFG_CMD_NET, FEC_ENET & NET_MULTI */
-#endif /* CONFIG_MCFFEC */
projects / J-u-boot.git / blobdiff