Merge tag 'u-boot-at91-2022.04-a' of https://source.denx.de/u-boot/custodians/u-boot...

[J-u-boot.git] / include / virtex2.h

diff --git a/include/virtex2.h b/include/virtex2.h
index 4717e0c2826fb4bbca85d882e897649ecdc049c7..7e8d93f24da45d094ef379f04ae948021a35f6d1 100644 (file)
--- a/include/virtex2.h
+++ b/include/virtex2.h
@@ -1,26 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2002
  * Rich Ireland, Enterasys Networks, [email protected].
  * Keith Outwater, [email protected]
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
  */
 
 #ifndef _VIRTEX2_H_
@@ -28,43 +10,39 @@
 
 #include <xilinx.h>
 
-extern int Virtex2_load(Xilinx_desc *desc, const void *image, size_t size);
-extern int Virtex2_dump(Xilinx_desc *desc, const void *buf, size_t bsize);
-extern int Virtex2_info(Xilinx_desc *desc);
-
 /*
- * Slave SelectMap Implementation function table.
+ * Slave SelectMap or Serial Implementation function table.
  */
 typedef struct {
-       Xilinx_pre_fn   pre;
-       Xilinx_pgm_fn   pgm;
-       Xilinx_init_fn  init;
-       Xilinx_err_fn   err;
-       Xilinx_done_fn  done;
-       Xilinx_clk_fn   clk;
-       Xilinx_cs_fn    cs;
-       Xilinx_wr_fn    wr;
-       Xilinx_rdata_fn rdata;
-       Xilinx_wdata_fn wdata;
-       Xilinx_busy_fn  busy;
-       Xilinx_abort_fn abort;
-       Xilinx_post_fn  post;
-} Xilinx_Virtex2_Slave_SelectMap_fns;
-
-/* Slave Serial Implementation function table */
-typedef struct {
-       Xilinx_pgm_fn   pgm;
-       Xilinx_clk_fn   clk;
-       Xilinx_rdata_fn rdata;
-       Xilinx_wdata_fn wdata;
-} Xilinx_Virtex2_Slave_Serial_fns;
+       xilinx_pre_fn   pre;
+       xilinx_pgm_fn   pgm;
+       xilinx_init_fn  init;
+       xilinx_err_fn   err;
+       xilinx_done_fn  done;
+       xilinx_clk_fn   clk;
+       xilinx_cs_fn    cs;
+       xilinx_wr_fn    wr;
+       xilinx_rdata_fn rdata;
+       xilinx_wdata_fn wdata;
+       xilinx_bwr_fn   wbulkdata;
+       xilinx_busy_fn  busy;
+       xilinx_abort_fn abort;
+       xilinx_post_fn  post;
+} xilinx_virtex2_slave_fns;
+
+#if defined(CONFIG_FPGA_VIRTEX2)
+extern struct xilinx_fpga_op virtex2_op;
+# define FPGA_VIRTEX2_OPS      &virtex2_op
+#else
+# define FPGA_VIRTEX2_OPS      NULL
+#endif
 
 /* Device Image Sizes (in bytes)
  *********************************************************************/
-#define XILINX_XC2V40_SIZE             (338208 / 8)
-#define XILINX_XC2V80_SIZE             (597408 / 8)
-#define XILINX_XC2V250_SIZE            (1591584 / 8)
-#define XILINX_XC2V500_SIZE            (2557857 / 8)
+#define XILINX_XC2V40_SIZE     (338208 / 8)
+#define XILINX_XC2V80_SIZE     (597408 / 8)
+#define XILINX_XC2V250_SIZE    (1591584 / 8)
+#define XILINX_XC2V500_SIZE    (2557857 / 8)
 #define XILINX_XC2V1000_SIZE   (3749408 / 8)
 #define XILINX_XC2V1500_SIZE   (5166240 / 8)
 #define XILINX_XC2V2000_SIZE   (6808352 / 8)
@@ -77,39 +55,51 @@ typedef struct {
 /* Descriptor Macros
  *********************************************************************/
 #define XILINX_XC2V40_DESC(iface, fn_table, cookie)    \
-{ Xilinx_Virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \
+       FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \
+       FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \
+       FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \
+       FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \
+       FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \
+       FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \
+       FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \
+       FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \
+       FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \
+       FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \
+       FPGA_VIRTEX2_OPS }
 
 #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
-{ Xilinx_Virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie }
+{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \
+       FPGA_VIRTEX2_OPS }
 
 #endif /* _VIRTEX2_H_ */