Merge patch series "Misc. PowerPC MPC83xx fixes/cleanups"

[J-u-boot.git] / configs / chromebook_speedy_defconfig

diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig
index 2346c83aab4c90dbea24d5ee76e90266cdfe57b2..c19b0905d5cfde728ecfb8f5c5fd2bd35ee80483 100644 (file)
--- a/configs/chromebook_speedy_defconfig
+++ b/configs/chromebook_speedy_defconfig
@@ -9,7 +9,6 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000
 CONFIG_SF_DEFAULT_SPEED=20000000
 CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
-CONFIG_SPL_TEXT_BASE=0xff704000
 CONFIG_DM_RESET=y
 CONFIG_SYS_MONITOR_LEN=614400
 CONFIG_ROCKCHIP_RK3288=y
@@ -17,14 +16,18 @@ CONFIG_ROCKCHIP_RK3288=y
 CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
 CONFIG_SPL_STACK_R_ADDR=0x80000
 CONFIG_SPL_STACK=0xff718000
+CONFIG_SPL_TEXT_BASE=0xff704000
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_SYS_LOAD_ADDR=0x800800
+CONFIG_SF_DEFAULT_BUS=2
 CONFIG_DEBUG_UART_BASE=0xff690000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
-CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_SPL_PAYLOAD="u-boot.img"
 CONFIG_DEBUG_UART=y
-CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_USE_PREBOOT=y
 CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
 CONFIG_SILENT_CONSOLE=y
@@ -36,9 +39,6 @@ CONFIG_SPL_PAD_TO=0x7f8000
 CONFIG_SPL_NO_BSS_LIMIT=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
-# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
 CONFIG_CMD_GPIO=y
@@ -81,7 +81,6 @@ CONFIG_MMC_PWRSEQ=y
 # CONFIG_SPL_DM_MMC is not set
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_PINCTRL=y