ppc/85xx: Move code around to prep for NAND_SPL

[J-u-boot.git] / cpu / mpc85xx / tlb.c

diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c
index 3d15d50b85a1f863034b4470235b854defc2cbb0..44e80b1b74544b3d4ee0d9feea0c0c30abe56f3a 100644 (file)
--- a/cpu/mpc85xx/tlb.c
+++ b/cpu/mpc85xx/tlb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, [email protected].
@@ -26,6 +26,34 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
+#ifdef CONFIG_ADDR_MAP
+#include <addr_map.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void invalidate_tlb(u8 tlb)
+{
+       if (tlb == 0)
+               mtspr(MMUCSR0, 0x4);
+       if (tlb == 1)
+               mtspr(MMUCSR0, 0x2);
+}
+
+void init_tlbs(void)
+{
+       int i;
+
+       for (i = 0; i < num_tlb_entries; i++) {
+               write_tlb(tlb_table[i].mas0,
+                         tlb_table[i].mas1,
+                         tlb_table[i].mas2,
+                         tlb_table[i].mas3,
+                         tlb_table[i].mas7);
+       }
+
+       return ;
+}
 
 void set_tlb(u8 tlb, u32 epn, u64 rpn,
             u8 perms, u8 wimge,
@@ -37,16 +65,14 @@ void set_tlb(u8 tlb, u32 epn, u64 rpn,
        _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
        _mas2 = FSL_BOOKE_MAS2(epn, wimge);
        _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
-       _mas7 = rpn >> 32;
+       _mas7 = FSL_BOOKE_MAS7(rpn);
 
-       mtspr(MAS0, _mas0);
-       mtspr(MAS1, _mas1);
-       mtspr(MAS2, _mas2);
-       mtspr(MAS3, _mas3);
-#ifdef CONFIG_ENABLE_36BIT_PHYS
-       mtspr(MAS7, _mas7);
+       write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
+
+#ifdef CONFIG_ADDR_MAP
+       if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
+               addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel);
 #endif
-       asm volatile("isync;msync;tlbwe;isync");
 }
 
 void disable_tlb(u8 esel)
@@ -67,26 +93,119 @@ void disable_tlb(u8 esel)
        mtspr(MAS7, _mas7);
 #endif
        asm volatile("isync;msync;tlbwe;isync");
+
+#ifdef CONFIG_ADDR_MAP
+       if (gd->flags & GD_FLG_RELOC)
+               addrmap_set_entry(0, 0, 0, esel);
+#endif
 }
 
-void invalidate_tlb(u8 tlb)
+static void tlbsx (const volatile unsigned *addr)
 {
-       if (tlb == 0)
-               mtspr(MMUCSR0, 0x4);
-       if (tlb == 1)
-               mtspr(MMUCSR0, 0x2);
+       __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
 }
 
-void init_tlbs(void)
+/* return -1 if we didn't find anything */
+int find_tlb_idx(void *addr, u8 tlbsel)
+{
+       u32 _mas0, _mas1;
+
+       /* zero out Search PID, AS */
+       mtspr(MAS6, 0);
+
+       tlbsx(addr);
+
+       _mas0 = mfspr(MAS0);
+       _mas1 = mfspr(MAS1);
+
+       /* we found something, and its in the TLB we expect */
+       if ((MAS1_VALID & _mas1) &&
+               (MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) {
+               return ((_mas0 & MAS0_ESEL_MSK) >> 16);
+       }
+
+       return -1;
+}
+
+#ifdef CONFIG_ADDR_MAP
+void init_addr_map(void)
 {
        int i;
+       unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff;
 
-       for (i = 0; i < num_tlb_entries; i++) {
-               set_tlb(tlb_table[i].tlb, tlb_table[i].epn, tlb_table[i].rpn,
-                       tlb_table[i].perms, tlb_table[i].wimge,
-                       tlb_table[i].ts, tlb_table[i].esel, tlb_table[i].tsize,
-                       tlb_table[i].iprot);
+       /* walk all the entries */
+       for (i = 0; i < max_cam; i++) {
+               unsigned long epn;
+               u32 tsize, _mas1;
+               phys_addr_t rpn;
+
+               mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
+
+               asm volatile("tlbre;isync");
+               _mas1 = mfspr(MAS1);
+
+               /* if the entry isn't valid skip it */
+               if (!(_mas1 & MAS1_VALID))
+                       continue;
+
+               tsize = (_mas1 >> 8) & 0xf;
+               epn = mfspr(MAS2) & MAS2_EPN;
+               rpn = mfspr(MAS3) & MAS3_RPN;
+#ifdef CONFIG_ENABLE_36BIT_PHYS
+               rpn |= ((phys_addr_t)mfspr(MAS7)) << 32;
+#endif
+
+               addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i);
        }
 
        return ;
 }
+#endif
+
+#ifndef CONFIG_SYS_DDR_TLB_START
+#define CONFIG_SYS_DDR_TLB_START 8
+#endif
+
+unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
+{
+       unsigned int tlb_size;
+       unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
+       unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
+       unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
+       u64 size, memsize = (u64)memsize_in_meg << 20;
+
+       size = min(memsize, CONFIG_MAX_MEM_MAPPED);
+
+       /* Convert (4^max) kB to (2^max) bytes */
+       max_cam = max_cam * 2 + 10;
+
+       for (; size && ram_tlb_index < 16; ram_tlb_index++) {
+               u32 camsize = __ilog2_u64(size) & ~1U;
+               u32 align = __ilog2(ram_tlb_address) & ~1U;
+
+               if (align == -2) align = max_cam;
+               if (camsize > align)
+                       camsize = align;
+
+               if (camsize > max_cam)
+                       camsize = max_cam;
+
+               tlb_size = (camsize - 10) / 2;
+
+               set_tlb(1, ram_tlb_address, ram_tlb_address,
+                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
+                       0, ram_tlb_index, tlb_size, 1);
+
+               size -= 1ULL << camsize;
+               memsize -= 1ULL << camsize;
+               ram_tlb_address += 1UL << camsize;
+       }
+
+       if (memsize)
+               print_size(memsize, " left unmapped\n");
+
+       /*
+        * Confirm that the requested amount of memory was mapped.
+        */
+       return memsize_in_meg;
+}