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1 | /* | |
2 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | |
3 | * | |
4 | * Based on davinci_dvevm.h. Original Copyrights follow: | |
5 | * | |
6 | * Copyright (C) 2007 Sergey Kubushyn <[email protected]> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | #ifndef __CONFIG_H | |
24 | #define __CONFIG_H | |
25 | ||
26 | /* | |
27 | * Board | |
28 | */ | |
29 | #define CONFIG_DRIVER_TI_EMAC | |
30 | /* check if direct NOR boot config is used */ | |
31 | #ifndef CONFIG_DIRECT_NOR_BOOT | |
32 | #define CONFIG_USE_SPIFLASH | |
33 | #endif | |
34 | ||
35 | ||
36 | /* | |
37 | * SoC Configuration | |
38 | */ | |
39 | #define CONFIG_MACH_DAVINCI_DA850_EVM | |
40 | #define CONFIG_ARM926EJS /* arm926ejs CPU core */ | |
41 | #define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ | |
42 | #define CONFIG_SOC_DA850 /* TI DA850 SoC */ | |
43 | #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH | |
44 | #define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) | |
45 | #define CONFIG_SYS_OSCIN_FREQ 24000000 | |
46 | #define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE | |
47 | #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) | |
48 | #define CONFIG_SYS_HZ 1000 | |
49 | #define CONFIG_SYS_DA850_PLL_INIT | |
50 | #define CONFIG_SYS_DA850_DDR_INIT | |
51 | ||
52 | #ifdef CONFIG_DIRECT_NOR_BOOT | |
53 | #define CONFIG_ARCH_CPU_INIT | |
54 | #define CONFIG_DA8XX_GPIO | |
55 | #define CONFIG_SYS_TEXT_BASE 0x60000000 | |
56 | #define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) | |
57 | #define CONFIG_DA850_LOWLEVEL | |
58 | #else | |
59 | #define CONFIG_SYS_TEXT_BASE 0xc1080000 | |
60 | #endif | |
61 | ||
62 | /* | |
63 | * Memory Info | |
64 | */ | |
65 | #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ | |
66 | #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ | |
67 | #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ | |
68 | #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ | |
69 | ||
70 | /* memtest start addr */ | |
71 | #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) | |
72 | ||
73 | /* memtest will be run on 16MB */ | |
74 | #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) | |
75 | ||
76 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
77 | ||
78 | #define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ | |
79 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ | |
80 | DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ | |
81 | DAVINCI_SYSCFG_SUSPSRC_UART2 | \ | |
82 | DAVINCI_SYSCFG_SUSPSRC_EMAC | \ | |
83 | DAVINCI_SYSCFG_SUSPSRC_I2C) | |
84 | ||
85 | /* | |
86 | * PLL configuration | |
87 | */ | |
88 | #define CONFIG_SYS_DV_CLKMODE 0 | |
89 | #define CONFIG_SYS_DA850_PLL0_POSTDIV 1 | |
90 | #define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000 | |
91 | #define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001 | |
92 | #define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 | |
93 | #define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003 | |
94 | #define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002 | |
95 | #define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1 | |
96 | #define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005 | |
97 | ||
98 | #define CONFIG_SYS_DA850_PLL1_POSTDIV 1 | |
99 | #define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000 | |
100 | #define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001 | |
101 | #define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002 | |
102 | ||
103 | #define CONFIG_SYS_DA850_PLL0_PLLM 24 | |
104 | #define CONFIG_SYS_DA850_PLL1_PLLM 21 | |
105 | ||
106 | /* | |
107 | * DDR2 memory configuration | |
108 | */ | |
109 | #define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ | |
110 | DV_DDR_PHY_EXT_STRBEN | \ | |
111 | (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) | |
112 | ||
113 | #define CONFIG_SYS_DA850_DDR2_SDBCR ( \ | |
114 | (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ | |
115 | (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ | |
116 | (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ | |
117 | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ | |
118 | (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ | |
119 | (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ | |
120 | (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) | |
121 | ||
122 | /* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ | |
123 | #define CONFIG_SYS_DA850_DDR2_SDBCR2 0 | |
124 | ||
125 | #define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ | |
126 | (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ | |
127 | (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ | |
128 | (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ | |
129 | (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ | |
130 | (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ | |
131 | (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ | |
132 | (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ | |
133 | (0 << DV_DDR_SDTMR1_WTR_SHIFT)) | |
134 | ||
135 | #define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ | |
136 | (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ | |
137 | (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ | |
138 | (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ | |
139 | (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ | |
140 | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ | |
141 | (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ | |
142 | (0 << DV_DDR_SDTMR2_CKE_SHIFT)) | |
143 | ||
144 | #define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 | |
145 | #define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 | |
146 | ||
147 | /* | |
148 | * Serial Driver info | |
149 | */ | |
150 | #define CONFIG_SYS_NS16550 | |
151 | #define CONFIG_SYS_NS16550_SERIAL | |
152 | #define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */ | |
153 | #define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */ | |
154 | #define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) | |
155 | #define CONFIG_CONS_INDEX 1 /* use UART0 for console */ | |
156 | #define CONFIG_BAUDRATE 115200 /* Default baud rate */ | |
157 | ||
158 | #define CONFIG_SPI | |
159 | #define CONFIG_SPI_FLASH | |
160 | #define CONFIG_SPI_FLASH_STMICRO | |
161 | #define CONFIG_SPI_FLASH_WINBOND | |
162 | #define CONFIG_DAVINCI_SPI | |
163 | #define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE | |
164 | #define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) | |
165 | #define CONFIG_SF_DEFAULT_SPEED 30000000 | |
166 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
167 | ||
168 | #ifdef CONFIG_USE_SPIFLASH | |
169 | #define CONFIG_SPL_SPI_SUPPORT | |
170 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
171 | #define CONFIG_SPL_SPI_LOAD | |
172 | #define CONFIG_SPL_SPI_BUS 0 | |
173 | #define CONFIG_SPL_SPI_CS 0 | |
174 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000 | |
175 | #define CONFIG_SYS_SPI_U_BOOT_SIZE 0x30000 | |
176 | #endif | |
177 | ||
178 | /* | |
179 | * I2C Configuration | |
180 | */ | |
181 | #define CONFIG_HARD_I2C | |
182 | #define CONFIG_DRIVER_DAVINCI_I2C | |
183 | #define CONFIG_SYS_I2C_SPEED 25000 | |
184 | #define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ | |
185 | #define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 | |
186 | ||
187 | /* | |
188 | * Flash & Environment | |
189 | */ | |
190 | #ifdef CONFIG_USE_NAND | |
191 | #undef CONFIG_ENV_IS_IN_FLASH | |
192 | #define CONFIG_NAND_DAVINCI | |
193 | #define CONFIG_SYS_NO_FLASH | |
194 | #define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ | |
195 | #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ | |
196 | #define CONFIG_ENV_SIZE (128 << 10) | |
197 | #define CONFIG_SYS_NAND_USE_FLASH_BBT | |
198 | #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST | |
199 | #define CONFIG_SYS_NAND_PAGE_2K | |
200 | #define CONFIG_SYS_NAND_CS 3 | |
201 | #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE | |
202 | #define CONFIG_SYS_CLE_MASK 0x10 | |
203 | #define CONFIG_SYS_ALE_MASK 0x8 | |
204 | #undef CONFIG_SYS_NAND_HW_ECC | |
205 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ | |
206 | #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST | |
207 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
208 | #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) | |
209 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) | |
210 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x28000 | |
211 | #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 | |
212 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 | |
213 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST | |
214 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ | |
215 | CONFIG_SYS_NAND_U_BOOT_SIZE - \ | |
216 | CONFIG_SYS_MALLOC_LEN - \ | |
217 | GENERATED_GBL_DATA_SIZE) | |
218 | #define CONFIG_SYS_NAND_ECCPOS { \ | |
219 | 24, 25, 26, 27, 28, \ | |
220 | 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ | |
221 | 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ | |
222 | 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ | |
223 | 59, 60, 61, 62, 63 } | |
224 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
225 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 | |
226 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
227 | #define CONFIG_SYS_NAND_ECCBYTES 10 | |
228 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
229 | #define CONFIG_SPL_NAND_SUPPORT | |
230 | #define CONFIG_SPL_NAND_SIMPLE | |
231 | #define CONFIG_SPL_NAND_LOAD | |
232 | #endif | |
233 | ||
234 | /* | |
235 | * Network & Ethernet Configuration | |
236 | */ | |
237 | #ifdef CONFIG_DRIVER_TI_EMAC | |
238 | #define CONFIG_MII | |
239 | #define CONFIG_BOOTP_DEFAULT | |
240 | #define CONFIG_BOOTP_DNS | |
241 | #define CONFIG_BOOTP_DNS2 | |
242 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
243 | #define CONFIG_NET_RETRY_COUNT 10 | |
244 | #endif | |
245 | ||
246 | #ifdef CONFIG_USE_NOR | |
247 | #define CONFIG_ENV_IS_IN_FLASH | |
248 | #define CONFIG_FLASH_CFI_DRIVER | |
249 | #define CONFIG_SYS_FLASH_CFI | |
250 | #define CONFIG_SYS_FLASH_PROTECTION | |
251 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ | |
252 | #define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ | |
253 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_SECT_SZ * 3) | |
254 | #define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ | |
255 | #define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE | |
256 | #define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ | |
257 | #define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ | |
258 | + 3) | |
259 | #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ | |
260 | #endif | |
261 | ||
262 | #ifdef CONFIG_USE_SPIFLASH | |
263 | #undef CONFIG_ENV_IS_IN_FLASH | |
264 | #undef CONFIG_ENV_IS_IN_NAND | |
265 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
266 | #define CONFIG_ENV_SIZE (64 << 10) | |
267 | #define CONFIG_ENV_OFFSET (256 << 10) | |
268 | #define CONFIG_ENV_SECT_SIZE (64 << 10) | |
269 | #define CONFIG_SYS_NO_FLASH | |
270 | #endif | |
271 | ||
272 | /* | |
273 | * U-Boot general configuration | |
274 | */ | |
275 | #define CONFIG_MISC_INIT_R | |
276 | #define CONFIG_BOARD_EARLY_INIT_F | |
277 | #define CONFIG_BOOTFILE "uImage" /* Boot file name */ | |
278 | #define CONFIG_SYS_PROMPT "U-Boot > " /* Command Prompt */ | |
279 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
280 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
281 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
282 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ | |
283 | #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) | |
284 | #define CONFIG_VERSION_VARIABLE | |
285 | #define CONFIG_AUTO_COMPLETE | |
286 | #define CONFIG_SYS_HUSH_PARSER | |
287 | #define CONFIG_CMDLINE_EDITING | |
288 | #define CONFIG_SYS_LONGHELP | |
289 | #define CONFIG_CRC32_VERIFY | |
290 | #define CONFIG_MX_CYCLIC | |
291 | ||
292 | /* | |
293 | * Linux Information | |
294 | */ | |
295 | #define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) | |
296 | #define CONFIG_HWCONFIG /* enable hwconfig */ | |
297 | #define CONFIG_CMDLINE_TAG | |
298 | #define CONFIG_REVISION_TAG | |
299 | #define CONFIG_SETUP_MEMORY_TAGS | |
300 | #define CONFIG_BOOTARGS \ | |
301 | "mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp" | |
302 | #define CONFIG_BOOTDELAY 3 | |
303 | #define CONFIG_EXTRA_ENV_SETTINGS "hwconfig=dsp:wake=yes" | |
304 | ||
305 | /* | |
306 | * U-Boot commands | |
307 | */ | |
308 | #include <config_cmd_default.h> | |
309 | #define CONFIG_CMD_ENV | |
310 | #define CONFIG_CMD_ASKENV | |
311 | #define CONFIG_CMD_DHCP | |
312 | #define CONFIG_CMD_DIAG | |
313 | #define CONFIG_CMD_MII | |
314 | #define CONFIG_CMD_PING | |
315 | #define CONFIG_CMD_SAVES | |
316 | #define CONFIG_CMD_MEMORY | |
317 | ||
318 | #ifdef CONFIG_CMD_BDI | |
319 | #define CONFIG_CLOCKS | |
320 | #endif | |
321 | ||
322 | #ifndef CONFIG_DRIVER_TI_EMAC | |
323 | #undef CONFIG_CMD_NET | |
324 | #undef CONFIG_CMD_DHCP | |
325 | #undef CONFIG_CMD_MII | |
326 | #undef CONFIG_CMD_PING | |
327 | #endif | |
328 | ||
329 | #ifdef CONFIG_USE_NAND | |
330 | #undef CONFIG_CMD_FLASH | |
331 | #undef CONFIG_CMD_IMLS | |
332 | #define CONFIG_CMD_NAND | |
333 | ||
334 | #define CONFIG_CMD_MTDPARTS | |
335 | #define CONFIG_MTD_DEVICE | |
336 | #define CONFIG_MTD_PARTITIONS | |
337 | #define CONFIG_LZO | |
338 | #define CONFIG_RBTREE | |
339 | #define CONFIG_CMD_UBI | |
340 | #define CONFIG_CMD_UBIFS | |
341 | #endif | |
342 | ||
343 | #ifdef CONFIG_USE_SPIFLASH | |
344 | #undef CONFIG_CMD_IMLS | |
345 | #undef CONFIG_CMD_FLASH | |
346 | #define CONFIG_CMD_SPI | |
347 | #define CONFIG_CMD_SF | |
348 | #define CONFIG_CMD_SAVEENV | |
349 | #endif | |
350 | ||
351 | #if !defined(CONFIG_USE_NAND) && \ | |
352 | !defined(CONFIG_USE_NOR) && \ | |
353 | !defined(CONFIG_USE_SPIFLASH) | |
354 | #define CONFIG_ENV_IS_NOWHERE | |
355 | #define CONFIG_SYS_NO_FLASH | |
356 | #define CONFIG_ENV_SIZE (16 << 10) | |
357 | #undef CONFIG_CMD_IMLS | |
358 | #undef CONFIG_CMD_ENV | |
359 | #endif | |
360 | ||
361 | /* SD/MMC configuration */ | |
362 | #ifndef CONFIG_USE_NOR | |
363 | #define CONFIG_MMC | |
364 | #define CONFIG_DAVINCI_MMC_SD1 | |
365 | #define CONFIG_GENERIC_MMC | |
366 | #define CONFIG_DAVINCI_MMC | |
367 | #endif | |
368 | ||
369 | /* | |
370 | * Enable MMC commands only when | |
371 | * MMC support is present | |
372 | */ | |
373 | #ifdef CONFIG_MMC | |
374 | #define CONFIG_DOS_PARTITION | |
375 | #define CONFIG_CMD_EXT2 | |
376 | #define CONFIG_CMD_FAT | |
377 | #define CONFIG_CMD_MMC | |
378 | #endif | |
379 | ||
380 | #ifndef CONFIG_DIRECT_NOR_BOOT | |
381 | /* defines for SPL */ | |
382 | #define CONFIG_SPL | |
383 | #define CONFIG_SPL_FRAMEWORK | |
384 | #define CONFIG_SPL_BOARD_INIT | |
385 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ | |
386 | CONFIG_SYS_MALLOC_LEN) | |
387 | #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN | |
388 | #define CONFIG_SPL_SPI_SUPPORT | |
389 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
390 | #define CONFIG_SPL_SPI_LOAD | |
391 | #define CONFIG_SPL_SPI_BUS 0 | |
392 | #define CONFIG_SPL_SPI_CS 0 | |
393 | #define CONFIG_SPL_SERIAL_SUPPORT | |
394 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
395 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
396 | #define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" | |
397 | #define CONFIG_SPL_STACK 0x8001ff00 | |
398 | #define CONFIG_SPL_TEXT_BASE 0x80000000 | |
399 | #define CONFIG_SPL_MAX_SIZE 32768 | |
400 | #endif | |
401 | ||
402 | /* Load U-Boot Image From MMC */ | |
403 | #ifdef CONFIG_SPL_MMC_LOAD | |
404 | #define CONFIG_SPL_MMC_SUPPORT | |
405 | #define CONFIG_SPL_LIBDISK_SUPPORT | |
406 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x75 | |
407 | #undef CONFIG_SPL_SPI_SUPPORT | |
408 | #undef CONFIG_SPL_SPI_LOAD | |
409 | #endif | |
410 | ||
411 | /* additions for new relocation code, must added to all boards */ | |
412 | #define CONFIG_SYS_SDRAM_BASE 0xc0000000 | |
413 | ||
414 | #ifdef CONFIG_DIRECT_NOR_BOOT | |
415 | #define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 | |
416 | #else | |
417 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ | |
418 | GENERATED_GBL_DATA_SIZE) | |
419 | #endif /* CONFIG_DIRECT_NOR_BOOT */ | |
420 | #endif /* __CONFIG_H */ |