Git Repo - J-u-boot.git/blame_incremental - include/configs/socfpga

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Commit	Line	Data
	1	/*
	2	* Copyright (C) 2015 Stefan Roese <[email protected]>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6	#ifndef __CONFIG_SOCFPGA_SR1500_H__
	7	#define __CONFIG_SOCFPGA_SR1500_H__
	8
	9	#include <asm/arch/base_addr_ac5.h>
	10
	11	#define CONFIG_HW_WATCHDOG
	12
	13	/* Memory configurations */
	14	#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
	15
	16	/* Booting Linux */
	17	#define CONFIG_LOADADDR 0x01000000
	18	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	19
	20	/* Ethernet on SoC (EMAC) */
	21	#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
	22	/* The PHY is autodetected, so no MII PHY address is needed here */
	23	#define CONFIG_PHY_MARVELL
	24	#define PHY_ANEG_TIMEOUT 8000
	25
	26	/* Environment */
	27
	28	/* Enable SPI NOR flash reset, needed for SPI booting */
	29	#define CONFIG_SPI_N25Q256A_RESET
	30
	31	/*
	32	* Bootcounter
	33	*/
	34	#define CONFIG_BOOTCOUNT_LIMIT
	35	/* last 2 lwords in OCRAM */
	36	#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8
	37	#define CONFIG_SYS_BOOTCOUNT_BE
	38
	39	/* Environment setting for SPI flash */
	40	#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
	41	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	42	#define CONFIG_ENV_SIZE (16 * 1024)
	43	#define CONFIG_ENV_OFFSET 0x000e0000
	44	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
	45	#define CONFIG_ENV_SPI_BUS 0
	46	#define CONFIG_ENV_SPI_CS 0
	47	#define CONFIG_ENV_SPI_MODE SPI_MODE_3
	48	#define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */
	49	#define CONFIG_SF_DEFAULT_SPEED 100000000
	50
	51	/*
	52	* The QSPI NOR flash layout on SR1500:
	53	*
	54	* 0000.0000 - 0003.ffff: SPL (4 times)
	55	* 0004.0000 - 000d.ffff: U-Boot
	56	* 000e.0000 - 000e.ffff: env1
	57	* 000f.0000 - 000f.ffff: env2
	58	*/
	59
	60	/* The rest of the configuration is shared */
	61	#include <configs/socfpga_common.h>
	62
	63	#endif /* __CONFIG_SOCFPGA_SR1500_H__ */