| | 1 | /* |
| | 2 | * (C) Copyright 2002 |
| | 3 | * Kyle Harris, Nexus Technologies, Inc. [email protected] |
| | 4 | * |
| | 5 | * (C) Copyright 2002 |
| | 6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| | 7 | * Marius Groeger <[email protected]> |
| | 8 | * |
| | 9 | * See file CREDITS for list of people who contributed to this |
| | 10 | * project. |
| | 11 | * |
| | 12 | * This program is free software; you can redistribute it and/or |
| | 13 | * modify it under the terms of the GNU General Public License as |
| | 14 | * published by the Free Software Foundation; either version 2 of |
| | 15 | * the License, or (at your option) any later version. |
| | 16 | * |
| | 17 | * This program is distributed in the hope that it will be useful, |
| | 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| | 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| | 20 | * GNU General Public License for more details. |
| | 21 | * |
| | 22 | * You should have received a copy of the GNU General Public License |
| | 23 | * along with this program; if not, write to the Free Software |
| | 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| | 25 | * MA 02111-1307 USA |
| | 26 | */ |
| | 27 | |
| | 28 | #ifndef __CONFIG_H |
| | 29 | #define __CONFIG_H |
| | 30 | |
| | 31 | /* |
| | 32 | * High Level Configuration Options |
| | 33 | * (easy to change) |
| | 34 | */ |
| | 35 | #define CONFIG_PXA250 1 /* This is an PXA250 CPU */ |
| | 36 | #define CONFIG_HHP_CRADLE 1 /* on an Cradle Board */ |
| | 37 | |
| | 38 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ |
| | 39 | |
| | 40 | /* we will never enable dcache, because we have to setup MMU first */ |
| | 41 | #define CONFIG_SYS_NO_DCACHE |
| | 42 | |
| | 43 | /* |
| | 44 | * Size of malloc() pool |
| | 45 | */ |
| | 46 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
| | 47 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
| | 48 | |
| | 49 | /* |
| | 50 | * Hardware drivers |
| | 51 | */ |
| | 52 | #define CONFIG_DRIVER_SMC91111 |
| | 53 | #define CONFIG_SMC91111_BASE 0x10000300 |
| | 54 | #define CONFIG_SMC91111_EXT_PHY |
| | 55 | #define CONFIG_SMC_USE_32_BIT |
| | 56 | |
| | 57 | /* |
| | 58 | * select serial console configuration |
| | 59 | */ |
| | 60 | #define CONFIG_PXA_SERIAL |
| | 61 | #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ |
| | 62 | |
| | 63 | /* allow to overwrite serial and ethaddr */ |
| | 64 | #define CONFIG_ENV_OVERWRITE |
| | 65 | |
| | 66 | #define CONFIG_BAUDRATE 115200 |
| | 67 | |
| | 68 | |
| | 69 | /* |
| | 70 | * BOOTP options |
| | 71 | */ |
| | 72 | #define CONFIG_BOOTP_BOOTFILESIZE |
| | 73 | #define CONFIG_BOOTP_BOOTPATH |
| | 74 | #define CONFIG_BOOTP_GATEWAY |
| | 75 | #define CONFIG_BOOTP_HOSTNAME |
| | 76 | |
| | 77 | |
| | 78 | /* |
| | 79 | * Command line configuration. |
| | 80 | */ |
| | 81 | #include <config_cmd_default.h> |
| | 82 | |
| | 83 | |
| | 84 | #define CONFIG_BOOTDELAY 3 |
| | 85 | #define CONFIG_BOOTARGS "root=/dev/mtdblock2 console=ttyS0,115200" |
| | 86 | #define CONFIG_ETHADDR 08:00:3e:26:0a:5b |
| | 87 | #define CONFIG_NETMASK 255.255.0.0 |
| | 88 | #define CONFIG_IPADDR 192.168.0.21 |
| | 89 | #define CONFIG_SERVERIP 192.168.0.250 |
| | 90 | #define CONFIG_BOOTCOMMAND "bootm 40000" |
| | 91 | #define CONFIG_CMDLINE_TAG |
| | 92 | |
| | 93 | /* |
| | 94 | * Miscellaneous configurable options |
| | 95 | */ |
| | 96 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| | 97 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
| | 98 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| | 99 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| | 100 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| | 101 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| | 102 | |
| | 103 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ |
| | 104 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ |
| | 105 | |
| | 106 | #define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ |
| | 107 | |
| | 108 | #define CONFIG_SYS_HZ 1000 |
| | 109 | #define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ |
| | 110 | |
| | 111 | /* valid baudrates */ |
| | 112 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| | 113 | |
| | 114 | /* |
| | 115 | * Stack sizes |
| | 116 | * |
| | 117 | * The stack sizes are set up in start.S using the settings below |
| | 118 | */ |
| | 119 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ |
| | 120 | #ifdef CONFIG_USE_IRQ |
| | 121 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ |
| | 122 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ |
| | 123 | #endif |
| | 124 | |
| | 125 | /* |
| | 126 | * Physical Memory Map |
| | 127 | */ |
| | 128 | #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ |
| | 129 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ |
| | 130 | #define PHYS_SDRAM_1_SIZE 0x01000000 /* 64 MB */ |
| | 131 | #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ |
| | 132 | #define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ |
| | 133 | #define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ |
| | 134 | #define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ |
| | 135 | #define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ |
| | 136 | #define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ |
| | 137 | |
| | 138 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
| | 139 | #define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ |
| | 140 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ |
| | 141 | |
| | 142 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 |
| | 143 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 |
| | 144 | |
| | 145 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
| | 146 | |
| | 147 | /* |
| | 148 | * FLASH and environment organization |
| | 149 | */ |
| | 150 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| | 151 | #define CONFIG_SYS_MAX_FLASH_SECT 32 /* max number of sectors on one chip */ |
| | 152 | |
| | 153 | /* timeout values are in ticks */ |
| | 154 | #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
| | 155 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
| | 156 | |
| | 157 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| | 158 | #define CONFIG_ENV_ADDR 0x00020000 /* absolute address for now */ |
| | 159 | #define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */ |
| | 160 | |
| | 161 | /****************************************************************************** |
| | 162 | * |
| | 163 | * CPU specific defines |
| | 164 | * |
| | 165 | ******************************************************************************/ |
| | 166 | |
| | 167 | /* |
| | 168 | * GPIO settings |
| | 169 | * |
| | 170 | * GPIO pin assignments |
| | 171 | * GPIO Name Dir Out AF |
| | 172 | * 0 NC |
| | 173 | * 1 NC |
| | 174 | * 2 SIRQ1 I |
| | 175 | * 3 SIRQ2 I |
| | 176 | * 4 SIRQ3 I |
| | 177 | * 5 DMAACK1 O 0 |
| | 178 | * 6 DMAACK2 O 0 |
| | 179 | * 7 DMAACK3 O 0 |
| | 180 | * 8 TC1 O 0 |
| | 181 | * 9 TC2 O 0 |
| | 182 | * 10 TC3 O 0 |
| | 183 | * 11 nDMAEN O 1 |
| | 184 | * 12 AENCTRL O 0 |
| | 185 | * 13 PLDTC O 0 |
| | 186 | * 14 ETHIRQ I |
| | 187 | * 15 NC |
| | 188 | * 16 NC |
| | 189 | * 17 NC |
| | 190 | * 18 RDY I |
| | 191 | * 19 DMASIO I |
| | 192 | * 20 ETHIRQ NC |
| | 193 | * 21 NC |
| | 194 | * 22 PGMEN O 1 FIXME for debug only enable flash |
| | 195 | * 23 NC |
| | 196 | * 24 NC |
| | 197 | * 25 NC |
| | 198 | * 26 NC |
| | 199 | * 27 NC |
| | 200 | * 28 NC |
| | 201 | * 29 NC |
| | 202 | * 30 NC |
| | 203 | * 31 NC |
| | 204 | * 32 NC |
| | 205 | * 33 NC |
| | 206 | * 34 FFRXD I 01 |
| | 207 | * 35 FFCTS I 01 |
| | 208 | * 36 FFDCD I 01 |
| | 209 | * 37 FFDSR I 01 |
| | 210 | * 38 FFRI I 01 |
| | 211 | * 39 FFTXD O 1 10 |
| | 212 | * 40 FFDTR O 0 10 |
| | 213 | * 41 FFRTS O 0 10 |
| | 214 | * 42 RS232FOFF O 0 00 |
| | 215 | * 43 NC |
| | 216 | * 44 NC |
| | 217 | * 45 IRSL0 O 0 |
| | 218 | * 46 IRRX0 I 01 |
| | 219 | * 47 IRTX0 O 0 10 |
| | 220 | * 48 NC |
| | 221 | * 49 nIOWE O 0 |
| | 222 | * 50 NC |
| | 223 | * 51 NC |
| | 224 | * 52 NC |
| | 225 | * 53 NC |
| | 226 | * 54 NC |
| | 227 | * 55 NC |
| | 228 | * 56 NC |
| | 229 | * 57 NC |
| | 230 | * 58 DKDIRQ I |
| | 231 | * 59 NC |
| | 232 | * 60 NC |
| | 233 | * 61 NC |
| | 234 | * 62 NC |
| | 235 | * 63 NC |
| | 236 | * 64 COMLED O 0 |
| | 237 | * 65 COMLED O 0 |
| | 238 | * 66 COMLED O 0 |
| | 239 | * 67 COMLED O 0 |
| | 240 | * 68 COMLED O 0 |
| | 241 | * 69 COMLED O 0 |
| | 242 | * 70 COMLED O 0 |
| | 243 | * 71 COMLED O 0 |
| | 244 | * 72 NC |
| | 245 | * 73 NC |
| | 246 | * 74 NC |
| | 247 | * 75 NC |
| | 248 | * 76 NC |
| | 249 | * 77 NC |
| | 250 | * 78 CSIO O 1 |
| | 251 | * 79 NC |
| | 252 | * 80 CSETH O 1 |
| | 253 | * |
| | 254 | * NOTE: All NC's are defined to be outputs |
| | 255 | * |
| | 256 | */ |
| | 257 | /* Pin direction control */ |
| | 258 | /* NOTE GPIO 0, 61, 62 are set for inputs due to CPLD SPAREs */ |
| | 259 | #define CONFIG_SYS_GPDR0_VAL 0xfff3bf02 |
| | 260 | #define CONFIG_SYS_GPDR1_VAL 0xfbffbf83 |
| | 261 | #define CONFIG_SYS_GPDR2_VAL 0x0001ffff |
| | 262 | /* Set and Clear registers */ |
| | 263 | #define CONFIG_SYS_GPSR0_VAL 0x00400800 |
| | 264 | #define CONFIG_SYS_GPSR1_VAL 0x00000480 |
| | 265 | #define CONFIG_SYS_GPSR2_VAL 0x00014000 |
| | 266 | #define CONFIG_SYS_GPCR0_VAL 0x00000000 |
| | 267 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 |
| | 268 | #define CONFIG_SYS_GPCR2_VAL 0x00000000 |
| | 269 | /* Edge detect registers (these are set by the kernel) */ |
| | 270 | #define CONFIG_SYS_GRER0_VAL 0x00000000 |
| | 271 | #define CONFIG_SYS_GRER1_VAL 0x00000000 |
| | 272 | #define CONFIG_SYS_GRER2_VAL 0x00000000 |
| | 273 | #define CONFIG_SYS_GFER0_VAL 0x00000000 |
| | 274 | #define CONFIG_SYS_GFER1_VAL 0x00000000 |
| | 275 | #define CONFIG_SYS_GFER2_VAL 0x00000000 |
| | 276 | /* Alternate function registers */ |
| | 277 | #define CONFIG_SYS_GAFR0_L_VAL 0x00000000 |
| | 278 | #define CONFIG_SYS_GAFR0_U_VAL 0x00000010 |
| | 279 | #define CONFIG_SYS_GAFR1_L_VAL 0x900a9550 |
| | 280 | #define CONFIG_SYS_GAFR1_U_VAL 0x00000008 |
| | 281 | #define CONFIG_SYS_GAFR2_L_VAL 0x20000000 |
| | 282 | #define CONFIG_SYS_GAFR2_U_VAL 0x00000002 |
| | 283 | |
| | 284 | /* |
| | 285 | * Clocks, power control and interrupts |
| | 286 | */ |
| | 287 | #define CONFIG_SYS_PSSR_VAL 0x00000020 |
| | 288 | #define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */ |
| | 289 | #define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */ |
| | 290 | #define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */ |
| | 291 | |
| | 292 | /* FIXME |
| | 293 | * |
| | 294 | * RTC settings |
| | 295 | * Watchdog |
| | 296 | * |
| | 297 | */ |
| | 298 | |
| | 299 | /* |
| | 300 | * Memory settings |
| | 301 | * |
| | 302 | * FIXME Can ethernet be burst read and/or write?? This is set for lubbock |
| | 303 | * Verify timings on all |
| | 304 | */ |
| | 305 | #define CONFIG_SYS_MSC0_VAL 0x000023FA /* flash bank (cs0) */ |
| | 306 | /*#define CONFIG_SYS_MSC1_VAL 0x00003549 / * SuperIO bank (cs2) */ |
| | 307 | #define CONFIG_SYS_MSC1_VAL 0x0000354c /* SuperIO bank (cs2) */ |
| | 308 | #define CONFIG_SYS_MSC2_VAL 0x00001224 /* Ethernet bank (cs4) */ |
| | 309 | #ifdef REDBOOT_WAY |
| | 310 | #define CONFIG_SYS_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ |
| | 311 | #define CONFIG_SYS_MDMRS_VAL 0x00000000 |
| | 312 | #define CONFIG_SYS_MDREFR_VAL 0x00018018 |
| | 313 | #else |
| | 314 | #define CONFIG_SYS_MDCNFG_VAL 0x00001aa1 /* FIXME can DTC be 01? */ |
| | 315 | #define CONFIG_SYS_MDMRS_VAL 0x00000000 |
| | 316 | #define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual bits set in lowlevel_init.S */ |
| | 317 | #endif |
| | 318 | |
| | 319 | /* |
| | 320 | * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) |
| | 321 | */ |
| | 322 | #define CONFIG_SYS_MECR_VAL 0x00000000 |
| | 323 | #define CONFIG_SYS_MCMEM0_VAL 0x00010504 |
| | 324 | #define CONFIG_SYS_MCMEM1_VAL 0x00010504 |
| | 325 | #define CONFIG_SYS_MCATT0_VAL 0x00010504 |
| | 326 | #define CONFIG_SYS_MCATT1_VAL 0x00010504 |
| | 327 | #define CONFIG_SYS_MCIO0_VAL 0x00004715 |
| | 328 | #define CONFIG_SYS_MCIO1_VAL 0x00004715 |
| | 329 | |
| | 330 | /* Board specific defines */ |
| | 331 | |
| | 332 | /* LED defines */ |
| | 333 | #define YELLOW 0x03 |
| | 334 | #define RED 0x02 |
| | 335 | #define GREEN 0x01 |
| | 336 | #define OFF 0x00 |
| | 337 | #define LED_IRDA0 0 |
| | 338 | #define LED_IRDA1 2 |
| | 339 | #define LED_IRDA2 4 |
| | 340 | #define LED_IRDA3 6 |
| | 341 | #define CRADLE_LED_SET_REG GPSR2 |
| | 342 | #define CRADLE_LED_CLR_REG GPCR2 |
| | 343 | |
| | 344 | /* SuperIO defines */ |
| | 345 | #define CRADLE_SIO_INDEX 0x2e |
| | 346 | #define CRADLE_SIO_DATA 0x2f |
| | 347 | |
| | 348 | /* IO defines */ |
| | 349 | #define CRADLE_CPLD_PHYS 0x08000000 |
| | 350 | #define CRADLE_SIO1_PHYS 0x08100000 |
| | 351 | #define CRADLE_SIO2_PHYS 0x08200000 |
| | 352 | #define CRADLE_SIO3_PHYS 0x08300000 |
| | 353 | #define CRADLE_ETH_PHYS 0x10000000 |
| | 354 | |
| | 355 | #ifndef __ASSEMBLY__ |
| | 356 | |
| | 357 | /* global prototypes */ |
| | 358 | void led_code(int code, int color); |
| | 359 | |
| | 360 | #endif |
| | 361 | |
| | 362 | #endif /* __CONFIG_H */ |
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