| | 1 | /* |
| | 2 | * (C) Copyright 2000 |
| | 3 | * Rob Taylor, Flying Pig Systems. [email protected]. |
| | 4 | * |
| | 5 | * See file CREDITS for list of people who contributed to this |
| | 6 | * project. |
| | 7 | * |
| | 8 | * This program is free software; you can redistribute it and/or |
| | 9 | * modify it under the terms of the GNU General Public License as |
| | 10 | * published by the Free Software Foundation; either version 2 of |
| | 11 | * the License, or (at your option) any later version. |
| | 12 | * |
| | 13 | * This program is distributed in the hope that it will be useful, |
| | 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| | 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| | 16 | * GNU General Public License for more details. |
| | 17 | * |
| | 18 | * You should have received a copy of the GNU General Public License |
| | 19 | * along with this program; if not, write to the Free Software |
| | 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| | 21 | * MA 02111-1307 USA |
| | 22 | */ |
| | 23 | |
| | 24 | /* winbond access routines and defines*/ |
| | 25 | |
| | 26 | /* from the winbond data sheet - |
| | 27 | The W83C553F SIO controller with PCI arbiter is a multi-function PCI device. |
| | 28 | Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller. |
| | 29 | */ |
| | 30 | |
| | 31 | /*ISA bridge configuration space*/ |
| | 32 | |
| | 33 | #define W83C553F_VID 0x10AD |
| | 34 | #define W83C553F_DID 0x0565 |
| | 35 | |
| | 36 | #define WINBOND_PCICONTR 0x40 /*pci control reg*/ |
| | 37 | #define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/ |
| | 38 | #define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/ |
| | 39 | #define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/ |
| | 40 | #define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/ |
| | 41 | #define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/ |
| | 42 | #define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/ |
| | 43 | #define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/ |
| | 44 | #define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/ |
| | 45 | #define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/ |
| | 46 | #define WINBOND_CDR 0x4c /*Clock Divisor Register*/ |
| | 47 | #define WINBOND_CSCR 0x4d /*Chip Select Control Register*/ |
| | 48 | #define WINBOND_ATSCR 0x4e /*AT System Control register*/ |
| | 49 | #define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/ |
| | 50 | #define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/ |
| | 51 | #define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/ |
| | 52 | #define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/ |
| | 53 | #define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/ |
| | 54 | |
| | 55 | #define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/ |
| | 56 | |
| | 57 | #define IPADCR_MBE512 0x1 |
| | 58 | #define IPADCR_MBE640 0x2 |
| | 59 | #define IPADCR_IPATOM4 0x10 |
| | 60 | #define IPADCR_IPATOM5 0x20 |
| | 61 | #define IPADCR_IPATOM6 0x40 |
| | 62 | #define IPADCR_IPATOM7 0x80 |
| | 63 | |
| | 64 | #define CSCR_UBIOSCSE 0x10 |
| | 65 | #define CSCR_BIOSWP 0x20 |
| | 66 | |
| | 67 | #define IDECSR_P0EN 0x01 |
| | 68 | #define IDECSR_P0F16 0x02 |
| | 69 | #define IDECSR_P1EN 0x10 |
| | 70 | #define IDECSR_P1F16 0x20 |
| | 71 | #define IDECSR_LEGIRQ 0x800 |
| | 72 | |
| | 73 | /* |
| | 74 | * Interrupt controller |
| | 75 | */ |
| | 76 | #define W83C553F_PIC1_ICW1 CONFIG_SYS_ISA_IO + 0x20 |
| | 77 | #define W83C553F_PIC1_ICW2 CONFIG_SYS_ISA_IO + 0x21 |
| | 78 | #define W83C553F_PIC1_ICW3 CONFIG_SYS_ISA_IO + 0x21 |
| | 79 | #define W83C553F_PIC1_ICW4 CONFIG_SYS_ISA_IO + 0x21 |
| | 80 | #define W83C553F_PIC1_OCW1 CONFIG_SYS_ISA_IO + 0x21 |
| | 81 | #define W83C553F_PIC1_OCW2 CONFIG_SYS_ISA_IO + 0x20 |
| | 82 | #define W83C553F_PIC1_OCW3 CONFIG_SYS_ISA_IO + 0x20 |
| | 83 | #define W83C553F_PIC1_ELC CONFIG_SYS_ISA_IO + 0x4D0 |
| | 84 | #define W83C553F_PIC2_ICW1 CONFIG_SYS_ISA_IO + 0xA0 |
| | 85 | #define W83C553F_PIC2_ICW2 CONFIG_SYS_ISA_IO + 0xA1 |
| | 86 | #define W83C553F_PIC2_ICW3 CONFIG_SYS_ISA_IO + 0xA1 |
| | 87 | #define W83C553F_PIC2_ICW4 CONFIG_SYS_ISA_IO + 0xA1 |
| | 88 | #define W83C553F_PIC2_OCW1 CONFIG_SYS_ISA_IO + 0xA1 |
| | 89 | #define W83C553F_PIC2_OCW2 CONFIG_SYS_ISA_IO + 0xA0 |
| | 90 | #define W83C553F_PIC2_OCW3 CONFIG_SYS_ISA_IO + 0xA0 |
| | 91 | #define W83C553F_PIC2_ELC CONFIG_SYS_ISA_IO + 0x4D1 |
| | 92 | |
| | 93 | #define W83C553F_TMR1_CMOD CONFIG_SYS_ISA_IO + 0x43 |
| | 94 | |
| | 95 | /* |
| | 96 | * DMA controller |
| | 97 | */ |
| | 98 | #define W83C553F_DMA1 CONFIG_SYS_ISA_IO + 0x000 /* channel 0 - 3 */ |
| | 99 | #define W83C553F_DMA2 CONFIG_SYS_ISA_IO + 0x0C0 /* channel 4 - 7 */ |
| | 100 | |
| | 101 | /* command/status register bit definitions */ |
| | 102 | |
| | 103 | #define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */ |
| | 104 | #define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */ |
| | 105 | #define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */ |
| | 106 | #define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */ |
| | 107 | |
| | 108 | #define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */ |
| | 109 | #define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */ |
| | 110 | #define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */ |
| | 111 | #define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */ |
| | 112 | |
| | 113 | #define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */ |
| | 114 | #define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */ |
| | 115 | #define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */ |
| | 116 | #define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */ |
| | 117 | |
| | 118 | /* mode register bit definitions */ |
| | 119 | |
| | 120 | #define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */ |
| | 121 | #define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */ |
| | 122 | #define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */ |
| | 123 | #define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */ |
| | 124 | #define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */ |
| | 125 | #define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */ |
| | 126 | #define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */ |
| | 127 | #define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */ |
| | 128 | #define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */ |
| | 129 | #define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */ |
| | 130 | #define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */ |
| | 131 | #define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */ |
| | 132 | #define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */ |
| | 133 | #define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */ |
| | 134 | |
| | 135 | /* request register bit definitions */ |
| | 136 | |
| | 137 | #define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */ |
| | 138 | #define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */ |
| | 139 | #define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */ |
| | 140 | #define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */ |
| | 141 | #define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */ |
| | 142 | |
| | 143 | /* write single mask bit register bit definitions */ |
| | 144 | |
| | 145 | #define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */ |
| | 146 | #define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */ |
| | 147 | #define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */ |
| | 148 | #define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */ |
| | 149 | #define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */ |
| | 150 | |
| | 151 | /* read/write all mask bits register bit definitions */ |
| | 152 | |
| | 153 | #define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */ |
| | 154 | #define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */ |
| | 155 | #define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */ |
| | 156 | #define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */ |
| | 157 | |
| | 158 | /* typedefs */ |
| | 159 | |
| | 160 | #define W83C553F_DMA1_CS 0x8 |
| | 161 | #define W83C553F_DMA1_WR 0x9 |
| | 162 | #define W83C553F_DMA1_WSMB 0xA |
| | 163 | #define W83C553F_DMA1_WM 0xB |
| | 164 | #define W83C553F_DMA1_CBP 0xC |
| | 165 | #define W83C553F_DMA1_MC 0xD |
| | 166 | #define W83C553F_DMA1_CM 0xE |
| | 167 | #define W83C553F_DMA1_RWAMB 0xF |
| | 168 | |
| | 169 | #define W83C553F_DMA2_CS 0x10 |
| | 170 | #define W83C553F_DMA2_WR 0x12 |
| | 171 | #define W83C553F_DMA2_WSMB 0x14 |
| | 172 | #define W83C553F_DMA2_WM 0x16 |
| | 173 | #define W83C553F_DMA2_CBP 0x18 |
| | 174 | #define W83C553F_DMA2_MC 0x1A |
| | 175 | #define W83C553F_DMA2_CM 0x1C |
| | 176 | #define W83C553F_DMA2_RWAMB 0x1E |
| | 177 | |
| | 178 | void initialise_w83c553f(void); |
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