| | 1 | /* |
| | 2 | * Copy and modify from linux/drivers/serial/sh-sci.h |
| | 3 | */ |
| | 4 | |
| | 5 | #include <dm/platform_data/serial_sh.h> |
| | 6 | |
| | 7 | struct uart_port { |
| | 8 | unsigned long iobase; /* in/out[bwl] */ |
| | 9 | unsigned char *membase; /* read/write[bwl] */ |
| | 10 | unsigned long mapbase; /* for ioremap */ |
| | 11 | enum sh_serial_type type; /* port type */ |
| | 12 | enum sh_clk_mode clk_mode; /* clock mode */ |
| | 13 | }; |
| | 14 | |
| | 15 | #if defined(CONFIG_CPU_SH7706) || \ |
| | 16 | defined(CONFIG_CPU_SH7707) || \ |
| | 17 | defined(CONFIG_CPU_SH7708) || \ |
| | 18 | defined(CONFIG_CPU_SH7709) |
| | 19 | # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ |
| | 20 | # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ |
| | 21 | # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
| | 22 | #elif defined(CONFIG_CPU_SH7705) |
| | 23 | # define SCIF0 0xA4400000 |
| | 24 | # define SCIF2 0xA4410000 |
| | 25 | # define SCSMR_Ir 0xA44A0000 |
| | 26 | # define IRDA_SCIF SCIF0 |
| | 27 | # define SCPCR 0xA4000116 |
| | 28 | # define SCPDR 0xA4000136 |
| | 29 | |
| | 30 | /* Set the clock source, |
| | 31 | * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input |
| | 32 | * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output |
| | 33 | */ |
| | 34 | # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 |
| | 35 | #elif defined(CONFIG_CPU_SH7720) || \ |
| | 36 | defined(CONFIG_CPU_SH7721) || \ |
| | 37 | defined(CONFIG_ARCH_SH7367) || \ |
| | 38 | defined(CONFIG_ARCH_SH7377) || \ |
| | 39 | defined(CONFIG_ARCH_SH7372) || \ |
| | 40 | defined(CONFIG_SH73A0) || \ |
| | 41 | defined(CONFIG_R8A7740) |
| | 42 | # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ |
| | 43 | # define PORT_PTCR 0xA405011EUL |
| | 44 | # define PORT_PVCR 0xA4050122UL |
| | 45 | # define SCIF_ORER 0x0200 /* overrun error bit */ |
| | 46 | #elif defined(CONFIG_SH_RTS7751R2D) |
| | 47 | # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ |
| | 48 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
| | 49 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| | 50 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| | 51 | #elif defined(CONFIG_CPU_SH7750) || \ |
| | 52 | defined(CONFIG_CPU_SH7750R) || \ |
| | 53 | defined(CONFIG_CPU_SH7750S) || \ |
| | 54 | defined(CONFIG_CPU_SH7091) || \ |
| | 55 | defined(CONFIG_CPU_SH7751) || \ |
| | 56 | defined(CONFIG_CPU_SH7751R) |
| | 57 | # define SCSPTR1 0xffe0001c /* 8 bit SCI */ |
| | 58 | # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
| | 59 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| | 60 | # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ |
| | 61 | 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \ |
| | 62 | 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */) |
| | 63 | #elif defined(CONFIG_CPU_SH7760) |
| | 64 | # define SCSPTR0 0xfe600024 /* 16 bit SCIF */ |
| | 65 | # define SCSPTR1 0xfe610024 /* 16 bit SCIF */ |
| | 66 | # define SCSPTR2 0xfe620024 /* 16 bit SCIF */ |
| | 67 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| | 68 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| | 69 | #elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) |
| | 70 | # define SCSPTR0 0xA4400000 /* 16 bit SCIF */ |
| | 71 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| | 72 | # define PACR 0xa4050100 |
| | 73 | # define PBCR 0xa4050102 |
| | 74 | # define SCSCR_INIT(port) 0x3B |
| | 75 | #elif defined(CONFIG_CPU_SH7343) |
| | 76 | # define SCSPTR0 0xffe00010 /* 16 bit SCIF */ |
| | 77 | # define SCSPTR1 0xffe10010 /* 16 bit SCIF */ |
| | 78 | # define SCSPTR2 0xffe20010 /* 16 bit SCIF */ |
| | 79 | # define SCSPTR3 0xffe30010 /* 16 bit SCIF */ |
| | 80 | # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ |
| | 81 | #elif defined(CONFIG_CPU_SH7722) |
| | 82 | # define PADR 0xA4050120 |
| | 83 | # undef PSDR |
| | 84 | # define PSDR 0xA405013e |
| | 85 | # define PWDR 0xA4050166 |
| | 86 | # define PSCR 0xA405011E |
| | 87 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| | 88 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| | 89 | #elif defined(CONFIG_CPU_SH7366) |
| | 90 | # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ |
| | 91 | # define SCSPTR0 SCPDR0 |
| | 92 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| | 93 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| | 94 | #elif defined(CONFIG_CPU_SH7723) |
| | 95 | # define SCSPTR0 0xa4050160 |
| | 96 | # define SCSPTR1 0xa405013e |
| | 97 | # define SCSPTR2 0xa4050160 |
| | 98 | # define SCSPTR3 0xa405013e |
| | 99 | # define SCSPTR4 0xa4050128 |
| | 100 | # define SCSPTR5 0xa4050128 |
| | 101 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| | 102 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| | 103 | #elif defined(CONFIG_CPU_SH7734) |
| | 104 | # define SCSPTR0 0xFFE40020 |
| | 105 | # define SCSPTR1 0xFFE41020 |
| | 106 | # define SCSPTR2 0xFFE42020 |
| | 107 | # define SCSPTR3 0xFFE43020 |
| | 108 | # define SCSPTR4 0xFFE44020 |
| | 109 | # define SCSPTR5 0xFFE45020 |
| | 110 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| | 111 | # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| | 112 | #elif defined(CONFIG_CPU_SH4_202) |
| | 113 | # define SCSPTR2 0xffe80020 /* 16 bit SCIF */ |
| | 114 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| | 115 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| | 116 | #elif defined(CONFIG_CPU_SH5_101) || defined(CONFIG_CPU_SH5_103) |
| | 117 | # define SCIF_BASE_ADDR 0x01030000 |
| | 118 | # define SCIF_ADDR_SH5 (PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR) |
| | 119 | # define SCIF_PTR2_OFFS 0x0000020 |
| | 120 | # define SCIF_LSR2_OFFS 0x0000024 |
| | 121 | # define SCSPTR\ |
| | 122 | ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ |
| | 123 | # define SCLSR2\ |
| | 124 | ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ |
| | 125 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ |
| | 126 | #elif defined(CONFIG_CPU_SH7757) || \ |
| | 127 | defined(CONFIG_CPU_SH7752) || \ |
| | 128 | defined(CONFIG_CPU_SH7753) |
| | 129 | # define SCSPTR0 0xfe4b0020 |
| | 130 | # define SCSPTR1 0xfe4b0020 |
| | 131 | # define SCSPTR2 0xfe4b0020 |
| | 132 | # define SCIF_ORER 0x0001 |
| | 133 | # define SCSCR_INIT(port) 0x38 |
| | 134 | # define SCIF_ONLY |
| | 135 | #elif defined(CONFIG_CPU_SH7763) |
| | 136 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ |
| | 137 | # define SCSPTR1 0xffe08024 /* 16 bit SCIF */ |
| | 138 | # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ |
| | 139 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| | 140 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| | 141 | #elif defined(CONFIG_CPU_SH7770) |
| | 142 | # define SCSPTR0 0xff923020 /* 16 bit SCIF */ |
| | 143 | # define SCSPTR1 0xff924020 /* 16 bit SCIF */ |
| | 144 | # define SCSPTR2 0xff925020 /* 16 bit SCIF */ |
| | 145 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| | 146 | # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ |
| | 147 | #elif defined(CONFIG_CPU_SH7780) |
| | 148 | # define SCSPTR0 0xffe00024 /* 16 bit SCIF */ |
| | 149 | # define SCSPTR1 0xffe10024 /* 16 bit SCIF */ |
| | 150 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
| | 151 | |
| | 152 | /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */ |
| | 153 | # define SCSCR_INIT(port) 0x3a |
| | 154 | |
| | 155 | #elif defined(CONFIG_CPU_SH7786) |
| | 156 | # define SCSPTR0 0xffea0024 /* 16 bit SCIF */ |
| | 157 | # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */ |
| | 158 | # define SCSPTR2 0xffec0024 /* 16 bit SCIF */ |
| | 159 | # define SCSPTR3 0xffed0024 /* 16 bit SCIF */ |
| | 160 | # define SCSPTR4 0xffee0024 /* 16 bit SCIF */ |
| | 161 | # define SCSPTR5 0xffef0024 /* 16 bit SCIF */ |
| | 162 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
| | 163 | # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| | 164 | #elif defined(CONFIG_CPU_SH7201) || \ |
| | 165 | defined(CONFIG_CPU_SH7203) || \ |
| | 166 | defined(CONFIG_CPU_SH7206) || \ |
| | 167 | defined(CONFIG_CPU_SH7263) || \ |
| | 168 | defined(CONFIG_CPU_SH7264) |
| | 169 | # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */ |
| | 170 | # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */ |
| | 171 | # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */ |
| | 172 | # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */ |
| | 173 | # if defined(CONFIG_CPU_SH7201) |
| | 174 | # define SCSPTR4 0xfffeA020 /* 16 bit SCIF */ |
| | 175 | # define SCSPTR5 0xfffeA820 /* 16 bit SCIF */ |
| | 176 | # define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ |
| | 177 | # define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ |
| | 178 | # endif |
| | 179 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| | 180 | #elif defined(CONFIG_CPU_SH7269) || defined(CONFIG_RZA1) |
| | 181 | # define SCSPTR0 0xe8007020 /* 16 bit SCIF */ |
| | 182 | # define SCSPTR1 0xe8007820 /* 16 bit SCIF */ |
| | 183 | # define SCSPTR2 0xe8008020 /* 16 bit SCIF */ |
| | 184 | # define SCSPTR3 0xe8008820 /* 16 bit SCIF */ |
| | 185 | # define SCSPTR4 0xe8009020 /* 16 bit SCIF */ |
| | 186 | # define SCSPTR5 0xe8009820 /* 16 bit SCIF */ |
| | 187 | # define SCSPTR6 0xe800a020 /* 16 bit SCIF */ |
| | 188 | # define SCSPTR7 0xe800a820 /* 16 bit SCIF */ |
| | 189 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| | 190 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| | 191 | #elif defined(CONFIG_CPU_SH7619) |
| | 192 | # define SCSPTR0 0xf8400020 /* 16 bit SCIF */ |
| | 193 | # define SCSPTR1 0xf8410020 /* 16 bit SCIF */ |
| | 194 | # define SCSPTR2 0xf8420020 /* 16 bit SCIF */ |
| | 195 | # define SCIF_ORER 0x0001 /* overrun error bit */ |
| | 196 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| | 197 | #elif defined(CONFIG_CPU_SHX3) |
| | 198 | # define SCSPTR0 0xffc30020 /* 16 bit SCIF */ |
| | 199 | # define SCSPTR1 0xffc40020 /* 16 bit SCIF */ |
| | 200 | # define SCSPTR2 0xffc50020 /* 16 bit SCIF */ |
| | 201 | # define SCSPTR3 0xffc60020 /* 16 bit SCIF */ |
| | 202 | # define SCIF_ORER 0x0001 /* Overrun error bit */ |
| | 203 | # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
| | 204 | #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_RCAR_GEN3) || \ |
| | 205 | defined(CONFIG_R7S72100) |
| | 206 | # if defined(CONFIG_SCIF_A) |
| | 207 | # define SCIF_ORER 0x0200 |
| | 208 | # else |
| | 209 | # define SCIF_ORER 0x0001 |
| | 210 | # endif |
| | 211 | # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) |
| | 212 | /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ |
| | 213 | #else |
| | 214 | # error CPU subtype not defined |
| | 215 | #endif |
| | 216 | |
| | 217 | /* SCSCR */ |
| | 218 | #define SCI_CTRL_FLAGS_TIE 0x80 /* all */ |
| | 219 | #define SCI_CTRL_FLAGS_RIE 0x40 /* all */ |
| | 220 | #define SCI_CTRL_FLAGS_TE 0x20 /* all */ |
| | 221 | #define SCI_CTRL_FLAGS_RE 0x10 /* all */ |
| | 222 | #if defined(CONFIG_CPU_SH7750) || \ |
| | 223 | defined(CONFIG_CPU_SH7091) || \ |
| | 224 | defined(CONFIG_CPU_SH7750R) || \ |
| | 225 | defined(CONFIG_CPU_SH7722) || \ |
| | 226 | defined(CONFIG_CPU_SH7734) || \ |
| | 227 | defined(CONFIG_CPU_SH7750S) || \ |
| | 228 | defined(CONFIG_CPU_SH7751) || \ |
| | 229 | defined(CONFIG_CPU_SH7751R) || \ |
| | 230 | defined(CONFIG_CPU_SH7763) || \ |
| | 231 | defined(CONFIG_CPU_SH7780) || \ |
| | 232 | defined(CONFIG_CPU_SH7786) || \ |
| | 233 | defined(CONFIG_CPU_SHX3) |
| | 234 | #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ |
| | 235 | #else |
| | 236 | #define SCI_CTRL_FLAGS_REIE 0 |
| | 237 | #endif |
| | 238 | /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
| | 239 | /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
| | 240 | /* SCI_CTRL_FLAGS_CKE1 0x02 * all */ |
| | 241 | /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ |
| | 242 | |
| | 243 | /* SCxSR SCI */ |
| | 244 | #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
| | 245 | #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
| | 246 | #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
| | 247 | #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
| | 248 | #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
| | 249 | #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
| | 250 | /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
| | 251 | /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
| | 252 | |
| | 253 | #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER) |
| | 254 | |
| | 255 | /* SCxSR SCIF */ |
| | 256 | #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ |
| | 257 | #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ |
| | 258 | #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ |
| | 259 | #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ |
| | 260 | #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ |
| | 261 | #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ |
| | 262 | #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ |
| | 263 | #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */ |
| | 264 | |
| | 265 | #if defined(CONFIG_CPU_SH7705) || \ |
| | 266 | defined(CONFIG_CPU_SH7720) || \ |
| | 267 | defined(CONFIG_CPU_SH7721) || \ |
| | 268 | defined(CONFIG_ARCH_SH7367) || \ |
| | 269 | defined(CONFIG_ARCH_SH7377) || \ |
| | 270 | defined(CONFIG_ARCH_SH7372) || \ |
| | 271 | defined(CONFIG_SH73A0) || \ |
| | 272 | defined(CONFIG_R8A7740) |
| | 273 | # define SCIF_ORER 0x0200 |
| | 274 | # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER) |
| | 275 | # define SCIF_RFDC_MASK 0x007f |
| | 276 | # define SCIF_TXROOM_MAX 64 |
| | 277 | #elif defined(CONFIG_CPU_SH7763) |
| | 278 | # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) |
| | 279 | # define SCIF_RFDC_MASK 0x007f |
| | 280 | # define SCIF_TXROOM_MAX 64 |
| | 281 | /* SH7763 SCIF2 support */ |
| | 282 | # define SCIF2_RFDC_MASK 0x001f |
| | 283 | # define SCIF2_TXROOM_MAX 16 |
| | 284 | #elif defined(CONFIG_RCAR_GEN2) |
| | 285 | # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) |
| | 286 | # if defined(CONFIG_SCIF_A) |
| | 287 | # define SCIF_RFDC_MASK 0x007f |
| | 288 | # else |
| | 289 | # define SCIF_RFDC_MASK 0x001f |
| | 290 | # endif |
| | 291 | #else |
| | 292 | # define SCIF_ERRORS (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK) |
| | 293 | # define SCIF_RFDC_MASK 0x001f |
| | 294 | # define SCIF_TXROOM_MAX 16 |
| | 295 | #endif |
| | 296 | |
| | 297 | #ifndef SCIF_ORER |
| | 298 | #define SCIF_ORER 0x0000 |
| | 299 | #endif |
| | 300 | |
| | 301 | #define SCxSR_TEND(port)\ |
| | 302 | (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) |
| | 303 | #define SCxSR_ERRORS(port)\ |
| | 304 | (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS) |
| | 305 | #define SCxSR_RDxF(port)\ |
| | 306 | (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) |
| | 307 | #define SCxSR_TDxE(port)\ |
| | 308 | (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) |
| | 309 | #define SCxSR_FER(port)\ |
| | 310 | (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) |
| | 311 | #define SCxSR_PER(port)\ |
| | 312 | (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) |
| | 313 | #define SCxSR_BRK(port)\ |
| | 314 | ((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) |
| | 315 | #define SCxSR_ORER(port)\ |
| | 316 | (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) |
| | 317 | |
| | 318 | #if defined(CONFIG_CPU_SH7705) || \ |
| | 319 | defined(CONFIG_CPU_SH7720) || \ |
| | 320 | defined(CONFIG_CPU_SH7721) || \ |
| | 321 | defined(CONFIG_ARCH_SH7367) || \ |
| | 322 | defined(CONFIG_ARCH_SH7377) || \ |
| | 323 | defined(CONFIG_ARCH_SH7372) || \ |
| | 324 | defined(CONFIG_SH73A0) || \ |
| | 325 | defined(CONFIG_R8A7740) |
| | 326 | # define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc) |
| | 327 | # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73) |
| | 328 | # define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf) |
| | 329 | # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3) |
| | 330 | #else |
| | 331 | # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc) |
| | 332 | # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073) |
| | 333 | # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df) |
| | 334 | # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3) |
| | 335 | #endif |
| | 336 | |
| | 337 | /* SCFCR */ |
| | 338 | #define SCFCR_RFRST 0x0002 |
| | 339 | #define SCFCR_TFRST 0x0004 |
| | 340 | #define SCFCR_TCRST 0x4000 |
| | 341 | #define SCFCR_MCE 0x0008 |
| | 342 | |
| | 343 | #define SCI_MAJOR 204 |
| | 344 | #define SCI_MINOR_START 8 |
| | 345 | |
| | 346 | /* Generic serial flags */ |
| | 347 | #define SCI_RX_THROTTLE 0x0000001 |
| | 348 | |
| | 349 | #define SCI_MAGIC 0xbabeface |
| | 350 | |
| | 351 | /* |
| | 352 | * Events are used to schedule things to happen at timer-interrupt |
| | 353 | * time, instead of at rs interrupt time. |
| | 354 | */ |
| | 355 | #define SCI_EVENT_WRITE_WAKEUP 0 |
| | 356 | |
| | 357 | #define SCI_IN(size, offset)\ |
| | 358 | if ((size) == 8) {\ |
| | 359 | return readb(port->membase + (offset));\ |
| | 360 | } else {\ |
| | 361 | return readw(port->membase + (offset));\ |
| | 362 | } |
| | 363 | #define SCI_OUT(size, offset, value)\ |
| | 364 | if ((size) == 8) {\ |
| | 365 | writeb(value, port->membase + (offset));\ |
| | 366 | } else if ((size) == 16) {\ |
| | 367 | writew(value, port->membase + (offset));\ |
| | 368 | } |
| | 369 | |
| | 370 | #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\ |
| | 371 | static inline unsigned int sci_##name##_in(struct uart_port *port) {\ |
| | 372 | if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ |
| | 373 | SCI_IN(scif_size, scif_offset)\ |
| | 374 | } else { /* PORT_SCI or PORT_SCIFA */\ |
| | 375 | SCI_IN(sci_size, sci_offset);\ |
| | 376 | }\ |
| | 377 | }\ |
| | 378 | static inline void sci_##name##_out(struct uart_port *port,\ |
| | 379 | unsigned int value) {\ |
| | 380 | if (port->type == PORT_SCIF || port->type == PORT_SCIFB) {\ |
| | 381 | SCI_OUT(scif_size, scif_offset, value)\ |
| | 382 | } else { /* PORT_SCI or PORT_SCIFA */\ |
| | 383 | SCI_OUT(sci_size, sci_offset, value);\ |
| | 384 | }\ |
| | 385 | } |
| | 386 | |
| | 387 | #define CPU_SCIF_FNS(name, scif_offset, scif_size) \ |
| | 388 | static inline unsigned int sci_##name##_in(struct uart_port *port) {\ |
| | 389 | SCI_IN(scif_size, scif_offset);\ |
| | 390 | }\ |
| | 391 | static inline void sci_##name##_out(struct uart_port *port,\ |
| | 392 | unsigned int value) {\ |
| | 393 | SCI_OUT(scif_size, scif_offset, value);\ |
| | 394 | } |
| | 395 | |
| | 396 | #define CPU_SCI_FNS(name, sci_offset, sci_size)\ |
| | 397 | static inline unsigned int sci_##name##_in(struct uart_port *port) {\ |
| | 398 | SCI_IN(sci_size, sci_offset);\ |
| | 399 | }\ |
| | 400 | static inline void sci_##name##_out(struct uart_port *port,\ |
| | 401 | unsigned int value) {\ |
| | 402 | SCI_OUT(sci_size, sci_offset, value);\ |
| | 403 | } |
| | 404 | |
| | 405 | #if defined(CONFIG_CPU_SH3) || \ |
| | 406 | defined(CONFIG_ARCH_SH7367) || \ |
| | 407 | defined(CONFIG_ARCH_SH7377) || \ |
| | 408 | defined(CONFIG_ARCH_SH7372) || \ |
| | 409 | defined(CONFIG_SH73A0) || \ |
| | 410 | defined(CONFIG_R8A7740) |
| | 411 | #if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712) |
| | 412 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ |
| | 413 | sh4_sci_offset, sh4_sci_size, \ |
| | 414 | sh3_scif_offset, sh3_scif_size, \ |
| | 415 | sh4_scif_offset, sh4_scif_size, \ |
| | 416 | h8_sci_offset, h8_sci_size) \ |
| | 417 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ |
| | 418 | sh4_scif_offset, sh4_scif_size) |
| | 419 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ |
| | 420 | sh4_scif_offset, sh4_scif_size) \ |
| | 421 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) |
| | 422 | #elif defined(CONFIG_CPU_SH7705) || \ |
| | 423 | defined(CONFIG_CPU_SH7720) || \ |
| | 424 | defined(CONFIG_CPU_SH7721) || \ |
| | 425 | defined(CONFIG_ARCH_SH7367) || \ |
| | 426 | defined(CONFIG_ARCH_SH7377) || \ |
| | 427 | defined(CONFIG_SH73A0) |
| | 428 | #define SCIF_FNS(name, scif_offset, scif_size) \ |
| | 429 | CPU_SCIF_FNS(name, scif_offset, scif_size) |
| | 430 | #elif defined(CONFIG_ARCH_SH7372) || \ |
| | 431 | defined(CONFIG_R8A7740) |
| | 432 | #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ |
| | 433 | sh4_scifb_offset, sh4_scifb_size) \ |
| | 434 | CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ |
| | 435 | sh4_scifb_offset, sh4_scifb_size) |
| | 436 | #define SCIF_FNS(name, scif_offset, scif_size) \ |
| | 437 | CPU_SCIF_FNS(name, scif_offset, scif_size) |
| | 438 | #else |
| | 439 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ |
| | 440 | sh4_sci_offset, sh4_sci_size, \ |
| | 441 | sh3_scif_offset, sh3_scif_size,\ |
| | 442 | sh4_scif_offset, sh4_scif_size, \ |
| | 443 | h8_sci_offset, h8_sci_size) \ |
| | 444 | CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ |
| | 445 | sh3_scif_offset, sh3_scif_size) |
| | 446 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\ |
| | 447 | sh4_scif_offset, sh4_scif_size) \ |
| | 448 | CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size) |
| | 449 | #endif |
| | 450 | #elif defined(CONFIG_CPU_SH7723) |
| | 451 | #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ |
| | 452 | sh4_scif_offset, sh4_scif_size) \ |
| | 453 | CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size,\ |
| | 454 | sh4_scif_offset, sh4_scif_size) |
| | 455 | #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ |
| | 456 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) |
| | 457 | #else |
| | 458 | #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\ |
| | 459 | sh4_sci_offset, sh4_sci_size, \ |
| | 460 | sh3_scif_offset, sh3_scif_size,\ |
| | 461 | sh4_scif_offset, sh4_scif_size, \ |
| | 462 | h8_sci_offset, h8_sci_size) \ |
| | 463 | CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\ |
| | 464 | sh4_scif_offset, sh4_scif_size) |
| | 465 | #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, \ |
| | 466 | sh4_scif_offset, sh4_scif_size) \ |
| | 467 | CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) |
| | 468 | #endif |
| | 469 | |
| | 470 | #if defined(CONFIG_CPU_SH7705) || \ |
| | 471 | defined(CONFIG_CPU_SH7720) || \ |
| | 472 | defined(CONFIG_CPU_SH7721) || \ |
| | 473 | defined(CONFIG_ARCH_SH7367) || \ |
| | 474 | defined(CONFIG_ARCH_SH7377) || \ |
| | 475 | defined(CONFIG_SH73A0) |
| | 476 | |
| | 477 | SCIF_FNS(SCSMR, 0x00, 16) |
| | 478 | SCIF_FNS(SCBRR, 0x04, 8) |
| | 479 | SCIF_FNS(SCSCR, 0x08, 16) |
| | 480 | SCIF_FNS(SCTDSR, 0x0c, 8) |
| | 481 | SCIF_FNS(SCFER, 0x10, 16) |
| | 482 | SCIF_FNS(SCxSR, 0x14, 16) |
| | 483 | SCIF_FNS(SCFCR, 0x18, 16) |
| | 484 | SCIF_FNS(SCFDR, 0x1c, 16) |
| | 485 | SCIF_FNS(SCxTDR, 0x20, 8) |
| | 486 | SCIF_FNS(SCxRDR, 0x24, 8) |
| | 487 | SCIF_FNS(SCLSR, 0x00, 0) |
| | 488 | SCIF_FNS(DL, 0x00, 0) /* dummy */ |
| | 489 | #elif defined(CONFIG_ARCH_SH7372) || \ |
| | 490 | defined(CONFIG_R8A7740) |
| | 491 | SCIF_FNS(SCSMR, 0x00, 16) |
| | 492 | SCIF_FNS(SCBRR, 0x04, 8) |
| | 493 | SCIF_FNS(SCSCR, 0x08, 16) |
| | 494 | SCIF_FNS(SCTDSR, 0x0c, 16) |
| | 495 | SCIF_FNS(SCFER, 0x10, 16) |
| | 496 | SCIF_FNS(SCxSR, 0x14, 16) |
| | 497 | SCIF_FNS(SCFCR, 0x18, 16) |
| | 498 | SCIF_FNS(SCFDR, 0x1c, 16) |
| | 499 | SCIF_FNS(SCTFDR, 0x38, 16) |
| | 500 | SCIF_FNS(SCRFDR, 0x3c, 16) |
| | 501 | SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) |
| | 502 | SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) |
| | 503 | SCIF_FNS(SCLSR, 0x00, 0) |
| | 504 | SCIF_FNS(DL, 0x00, 0) /* dummy */ |
| | 505 | #elif defined(CONFIG_CPU_SH7723) |
| | 506 | SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) |
| | 507 | SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) |
| | 508 | SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) |
| | 509 | SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) |
| | 510 | SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) |
| | 511 | SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) |
| | 512 | SCIx_FNS(SCSPTR, 0, 0, 0, 0) |
| | 513 | SCIF_FNS(SCTDSR, 0x0c, 8) |
| | 514 | SCIF_FNS(SCFER, 0x10, 16) |
| | 515 | SCIF_FNS(SCFCR, 0x18, 16) |
| | 516 | SCIF_FNS(SCFDR, 0x1c, 16) |
| | 517 | SCIF_FNS(SCLSR, 0x24, 16) |
| | 518 | SCIF_FNS(DL, 0x00, 0) /* dummy */ |
| | 519 | #elif defined(CONFIG_RCAR_GEN2) |
| | 520 | /* SCIFA and SCIF register offsets and size */ |
| | 521 | SCIx_FNS(SCSMR, 0, 0, 0x00, 16, 0, 0, 0x00, 16, 0, 0) |
| | 522 | SCIx_FNS(SCBRR, 0, 0, 0x04, 8, 0, 0, 0x04, 8, 0, 0) |
| | 523 | SCIx_FNS(SCSCR, 0, 0, 0x08, 16, 0, 0, 0x08, 16, 0, 0) |
| | 524 | SCIx_FNS(SCxTDR, 0, 0, 0x20, 8, 0, 0, 0x0C, 8, 0, 0) |
| | 525 | SCIx_FNS(SCxSR, 0, 0, 0x14, 16, 0, 0, 0x10, 16, 0, 0) |
| | 526 | SCIx_FNS(SCxRDR, 0, 0, 0x24, 8, 0, 0, 0x14, 8, 0, 0) |
| | 527 | SCIF_FNS(SCFCR, 0, 0, 0x18, 16) |
| | 528 | SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) |
| | 529 | SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) |
| | 530 | SCIF_FNS(DL, 0, 0, 0x30, 16) |
| | 531 | SCIF_FNS(CKS, 0, 0, 0x34, 16) |
| | 532 | #if defined(CONFIG_SCIF_A) |
| | 533 | SCIF_FNS(SCLSR, 0, 0, 0x14, 16) |
| | 534 | #else |
| | 535 | SCIF_FNS(SCLSR, 0, 0, 0x24, 16) |
| | 536 | #endif |
| | 537 | #else |
| | 538 | /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ |
| | 539 | /* name off sz off sz off sz off sz off sz*/ |
| | 540 | SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8) |
| | 541 | SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8) |
| | 542 | SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8) |
| | 543 | SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8) |
| | 544 | SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8) |
| | 545 | SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8) |
| | 546 | SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16) |
| | 547 | #if defined(CONFIG_CPU_SH7760) || \ |
| | 548 | defined(CONFIG_CPU_SH7780) || \ |
| | 549 | defined(CONFIG_CPU_SH7786) |
| | 550 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
| | 551 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) |
| | 552 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) |
| | 553 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) |
| | 554 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) |
| | 555 | #elif defined(CONFIG_CPU_SH7763) |
| | 556 | SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) |
| | 557 | SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) |
| | 558 | SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) |
| | 559 | SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) |
| | 560 | SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) |
| | 561 | SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) |
| | 562 | SCIF_FNS(SCLSR, 0, 0, 0x28, 16) |
| | 563 | #else |
| | 564 | |
| | 565 | SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) |
| | 566 | #if defined(CONFIG_CPU_SH7722) |
| | 567 | SCIF_FNS(SCSPTR, 0, 0, 0, 0) |
| | 568 | #else |
| | 569 | SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) |
| | 570 | #endif |
| | 571 | SCIF_FNS(SCLSR, 0, 0, 0x24, 16) |
| | 572 | #endif |
| | 573 | SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */ |
| | 574 | #endif |
| | 575 | #define sci_in(port, reg) sci_##reg##_in(port) |
| | 576 | #define sci_out(port, reg, value) sci_##reg##_out(port, value) |
| | 577 | |
| | 578 | #if defined(CONFIG_CPU_SH7706) || \ |
| | 579 | defined(CONFIG_CPU_SH7707) || \ |
| | 580 | defined(CONFIG_CPU_SH7708) || \ |
| | 581 | defined(CONFIG_CPU_SH7709) |
| | 582 | static inline int sci_rxd_in(struct uart_port *port) |
| | 583 | { |
| | 584 | if (port->mapbase == 0xfffffe80) |
| | 585 | return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ |
| | 586 | return 1; |
| | 587 | } |
| | 588 | #elif defined(CONFIG_CPU_SH7750) || \ |
| | 589 | defined(CONFIG_CPU_SH7751) || \ |
| | 590 | defined(CONFIG_CPU_SH7751R) || \ |
| | 591 | defined(CONFIG_CPU_SH7750R) || \ |
| | 592 | defined(CONFIG_CPU_SH7750S) || \ |
| | 593 | defined(CONFIG_CPU_SH7091) |
| | 594 | static inline int sci_rxd_in(struct uart_port *port) |
| | 595 | { |
| | 596 | if (port->mapbase == 0xffe00000) |
| | 597 | return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ |
| | 598 | return 1; |
| | 599 | } |
| | 600 | #else /* default case for non-SCI processors */ |
| | 601 | static inline int sci_rxd_in(struct uart_port *port) |
| | 602 | { |
| | 603 | return 1; |
| | 604 | } |
| | 605 | #endif |
| | 606 | |
| | 607 | /* |
| | 608 | * Values for the BitRate Register (SCBRR) |
| | 609 | * |
| | 610 | * The values are actually divisors for a frequency which can |
| | 611 | * be internal to the SH3 (14.7456MHz) or derived from an external |
| | 612 | * clock source. This driver assumes the internal clock is used; |
| | 613 | * to support using an external clock source, config options or |
| | 614 | * possibly command-line options would need to be added. |
| | 615 | * |
| | 616 | * Also, to support speeds below 2400 (why?) the lower 2 bits of |
| | 617 | * the SCSMR register would also need to be set to non-zero values. |
| | 618 | * |
| | 619 | * -- Greg Banks 27Feb2000 |
| | 620 | * |
| | 621 | * Answer: The SCBRR register is only eight bits, and the value in |
| | 622 | * it gets larger with lower baud rates. At around 2400 (depending on |
| | 623 | * the peripherial module clock) you run out of bits. However the |
| | 624 | * lower two bits of SCSMR allow the module clock to be divided down, |
| | 625 | * scaling the value which is needed in SCBRR. |
| | 626 | * |
| | 627 | * -- Stuart Menefy - 23 May 2000 |
| | 628 | * |
| | 629 | * I meant, why would anyone bother with bitrates below 2400. |
| | 630 | * |
| | 631 | * -- Greg Banks - 7Jul2000 |
| | 632 | * |
| | 633 | * You "speedist"! How will I use my 110bps ASR-33 teletype with paper |
| | 634 | * tape reader as a console! |
| | 635 | * |
| | 636 | * -- Mitch Davis - 15 Jul 2000 |
| | 637 | */ |
| | 638 | |
| | 639 | #if defined(CONFIG_CPU_SH7780) || \ |
| | 640 | defined(CONFIG_CPU_SH7786) |
| | 641 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) |
| | 642 | #elif defined(CONFIG_CPU_SH7705) || \ |
| | 643 | defined(CONFIG_CPU_SH7720) || \ |
| | 644 | defined(CONFIG_CPU_SH7721) || \ |
| | 645 | defined(CONFIG_ARCH_SH7367) || \ |
| | 646 | defined(CONFIG_ARCH_SH7377) || \ |
| | 647 | defined(CONFIG_ARCH_SH7372) || \ |
| | 648 | defined(CONFIG_SH73A0) || \ |
| | 649 | defined(CONFIG_R8A7740) |
| | 650 | #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |
| | 651 | #elif defined(CONFIG_CPU_SH7723) |
| | 652 | static inline int scbrr_calc(struct uart_port *port, int bps, int clk) |
| | 653 | { |
| | 654 | if (port->type == PORT_SCIF) |
| | 655 | return (clk+16*bps)/(32*bps)-1; |
| | 656 | else |
| | 657 | return ((clk*2)+16*bps)/(16*bps)-1; |
| | 658 | } |
| | 659 | #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) |
| | 660 | #elif defined(CONFIG_RCAR_GEN2) |
| | 661 | #define DL_VALUE(bps, clk) (clk / bps / 16) /* External Clock */ |
| | 662 | #if defined(CONFIG_SCIF_A) |
| | 663 | #define SCBRR_VALUE(bps, clk) (clk / bps / 16 - 1) /* Internal Clock */ |
| | 664 | #else |
| | 665 | #define SCBRR_VALUE(bps, clk) (clk / bps / 32 - 1) /* Internal Clock */ |
| | 666 | #endif |
| | 667 | #else /* Generic SH */ |
| | 668 | #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) |
| | 669 | #endif |
| | 670 | |
| | 671 | #ifndef DL_VALUE |
| | 672 | #define DL_VALUE(bps, clk) 0 |
| | 673 | #endif |
projects / J-u-boot.git / blame_incremental