Git Repo - J-u-boot.git/blame_incremental - configs/socfpga_vining_fpga

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Commit	Line	Data
	1	CONFIG_ARM=y
	2	CONFIG_SYS_L2_PL310=y
	3	CONFIG_ARCH_SOCFPGA=y
	4	CONFIG_SYS_MALLOC_LEN=0x4000000
	5	CONFIG_ENV_SIZE=0x4000
	6	CONFIG_ENV_OFFSET=0x100000
	7	CONFIG_ENV_SECT_SIZE=0x10000
	8	CONFIG_DM_GPIO=y
	9	CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_vining_fpga"
	10	CONFIG_SPL_TEXT_BASE=0xFFFF0000
	11	CONFIG_TARGET_SOCFPGA_SOFTING_VINING_FPGA=y
	12	CONFIG_ENV_OFFSET_REDUND=0x110000
	13	CONFIG_DISTRO_DEFAULTS=y
	14	CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
	15	CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000
	16	CONFIG_FIT=y
	17	CONFIG_TIMESTAMP=y
	18	CONFIG_BOOTDELAY=5
	19	CONFIG_USE_BOOTARGS=y
	20	CONFIG_BOOTARGS="console=ttyS0,115200"
	21	CONFIG_BOOTCOMMAND="run selboot"
	22	CONFIG_USE_PREBOOT=y
	23	CONFIG_PREBOOT="setenv hostname vining-${unit_serial} ; setenv PS1 \"${unit_ident} (${unit_serial}) => \" ; if gpio input 78 ; then setenv bootdelay 10 ; setenv boottype rcvr ; elif test -n \"$force_boottype\" ; then setenv bootdelay 1 ; setenv boottype \"$force_boottype\" ; setenv force_boottype ; saveenv ; else setenv bootdelay 5 ; setenv boottype norm ; fi"
	24	CONFIG_SYS_CONSOLE_IS_IN_ENV=y
	25	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
	26	CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
	27	# CONFIG_DISPLAY_BOARDINFO is not set
	28	CONFIG_DISPLAY_BOARDINFO_LATE=y
	29	CONFIG_CLOCKS=y
	30	CONFIG_MISC_INIT_R=y
	31	CONFIG_SPL_PAD_TO=0x10000
	32	CONFIG_SPL_NO_BSS_LIMIT=y
	33	# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
	34	CONFIG_SPL_STACK=0x0
	35	CONFIG_SPL_SPI_LOAD=y
	36	CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
	37	CONFIG_CMDLINE_PS_SUPPORT=y
	38	CONFIG_SYS_MAXARGS=32
	39	CONFIG_SYS_BOOTM_LEN=0x2000000
	40	CONFIG_CMD_ASKENV=y
	41	CONFIG_CMD_GREPENV=y
	42	CONFIG_CMD_EEPROM=y
	43	CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
	44	CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70
	45	CONFIG_CMD_DFU=y
	46	# CONFIG_CMD_FLASH is not set
	47	CONFIG_CMD_GPIO=y
	48	CONFIG_CMD_I2C=y
	49	CONFIG_CMD_MMC=y
	50	CONFIG_CMD_SPI=y
	51	CONFIG_CMD_USB=y
	52	CONFIG_CMD_USB_MASS_STORAGE=y
	53	CONFIG_CMD_CACHE=y
	54	CONFIG_CMD_TIME=y
	55	CONFIG_CMD_EXT4_WRITE=y
	56	CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
	57	CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),64k(env1),64k(env2),256k(softing1),256k(softing2),-(rcvrfs);"
	58	CONFIG_CMD_UBI=y
	59	# CONFIG_ISO_PARTITION is not set
	60	# CONFIG_EFI_PARTITION is not set
	61	CONFIG_ENV_IS_IN_SPI_FLASH=y
	62	CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
	63	CONFIG_SYS_RELOC_GD_ENV_ADDR=y
	64	CONFIG_USE_BOOTFILE=y
	65	CONFIG_BOOTFILE="fitImage"
	66	CONFIG_VERSION_VARIABLE=y
	67	CONFIG_BOOTP_SEND_HOSTNAME=y
	68	CONFIG_NET_RANDOM_ETHADDR=y
	69	CONFIG_SPL_DM_SEQ_ALIAS=y
	70	CONFIG_DFU_MMC=y
	71	CONFIG_DFU_RAM=y
	72	CONFIG_DFU_SF=y
	73	CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
	74	CONFIG_DWAPB_GPIO=y
	75	CONFIG_DM_I2C=y
	76	CONFIG_SYS_I2C_DW=y
	77	CONFIG_LED_STATUS=y
	78	CONFIG_LED_STATUS_GPIO=y
	79	CONFIG_LED_STATUS0=y
	80	CONFIG_LED_STATUS_BIT=48
	81	CONFIG_LED_STATUS1=y
	82	CONFIG_LED_STATUS_BIT1=53
	83	CONFIG_LED_STATUS2=y
	84	CONFIG_LED_STATUS_BIT2=54
	85	CONFIG_LED_STATUS3=y
	86	CONFIG_LED_STATUS_BIT3=65
	87	CONFIG_LED_STATUS_CMD=y
	88	CONFIG_MISC=y
	89	CONFIG_I2C_EEPROM=y
	90	CONFIG_SYS_I2C_EEPROM_ADDR=0x50
	91	CONFIG_MMC_DW=y
	92	CONFIG_MTD=y
	93	CONFIG_SF_DEFAULT_SPEED=40000000
	94	CONFIG_SPI_FLASH_SFDP_SUPPORT=y
	95	CONFIG_SPI_FLASH_SPANSION=y
	96	CONFIG_SPI_FLASH_STMICRO=y
	97	# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
	98	CONFIG_SPI_FLASH_MTD=y
	99	CONFIG_MTD_UBI_FASTMAP=y
	100	CONFIG_PHY_MICREL=y
	101	CONFIG_PHY_MICREL_KSZ90X1=y
	102	CONFIG_ETH_DESIGNWARE=y
	103	CONFIG_MII=y
	104	CONFIG_DM_RESET=y
	105	CONFIG_SPI=y
	106	CONFIG_CADENCE_QSPI=y
	107	CONFIG_DESIGNWARE_SPI=y
	108	CONFIG_USB=y
	109	CONFIG_USB_DWC2=y
	110	CONFIG_USB_GADGET=y
	111	CONFIG_USB_GADGET_MANUFACTURER="Softing"
	112	CONFIG_USB_GADGET_VENDOR_NUM=0x0525
	113	CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
	114	CONFIG_USB_GADGET_DWC2_OTG=y
	115	CONFIG_USB_GADGET_DOWNLOAD=y
	116	CONFIG_DESIGNWARE_WATCHDOG=y
	117	CONFIG_WDT=y