projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| d5dae85f MS |
2 | /* |
| 3 | * (C) Copyright 2012-2013, Xilinx, Michal Simek | |
| 4 | * | |
| 5 | * (C) Copyright 2012 | |
| 6 | * Joe Hershberger <[email protected]> | |
| d5dae85f MS |
7 | */ |
| 8 | ||
| 9 | #ifndef _ZYNQPL_H_ | |
| 10 | #define _ZYNQPL_H_ | |
| 11 | ||
| 12 | #include <xilinx.h> | |
| 13 | ||
| 37e3a36a | 14 | #ifdef CONFIG_CMD_ZYNQ_AES |
| 3427f4d2 SDPP |
15 | int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen, |
| 16 | u8 bstype); | |
| 37e3a36a SDPP |
17 | #endif |
| 18 | ||
| 14cfc4f3 | 19 | extern struct xilinx_fpga_op zynq_op; |
| d5dae85f | 20 | |
| 4aba5fb8 MS |
21 | #define XILINX_ZYNQ_XC7Z007S 0x3 |
| 22 | #define XILINX_ZYNQ_XC7Z010 0x2 | |
| 5389564b | 23 | #define XILINX_ZYNQ_XC7Z010_LR 0x4 |
| 4aba5fb8 MS |
24 | #define XILINX_ZYNQ_XC7Z012S 0x1c |
| 25 | #define XILINX_ZYNQ_XC7Z014S 0x8 | |
| 26 | #define XILINX_ZYNQ_XC7Z015 0x1b | |
| 5389564b | 27 | #define XILINX_ZYNQ_XC7Z020_LR 0x9 |
| 4aba5fb8 MS |
28 | #define XILINX_ZYNQ_XC7Z020 0x7 |
| 29 | #define XILINX_ZYNQ_XC7Z030 0xc | |
| 30 | #define XILINX_ZYNQ_XC7Z035 0x12 | |
| 31 | #define XILINX_ZYNQ_XC7Z045 0x11 | |
| 32 | #define XILINX_ZYNQ_XC7Z100 0x16 | |
| d5dae85f MS |
33 | |
| 34 | /* Device Image Sizes */ | |
| 05c59d0b | 35 | #define XILINX_XC7Z007S_SIZE 16669920/8 |
| d5dae85f | 36 | #define XILINX_XC7Z010_SIZE 16669920/8 |
| 5389564b | 37 | #define XILINX_XC7Z010_LR_SIZE 16669920/8 |
| 05c59d0b MS |
38 | #define XILINX_XC7Z012S_SIZE 28085344/8 |
| 39 | #define XILINX_XC7Z014S_SIZE 32364512/8 | |
| 31993d6a | 40 | #define XILINX_XC7Z015_SIZE 28085344/8 |
| 5389564b | 41 | #define XILINX_XC7Z020_LR_SIZE 32364512/8 |
| d5dae85f MS |
42 | #define XILINX_XC7Z020_SIZE 32364512/8 |
| 43 | #define XILINX_XC7Z030_SIZE 47839328/8 | |
| b9103809 | 44 | #define XILINX_XC7Z035_SIZE 106571232/8 |
| d5dae85f | 45 | #define XILINX_XC7Z045_SIZE 106571232/8 |
| fd2b10b6 | 46 | #define XILINX_XC7Z100_SIZE 139330784/8 |
| d5dae85f | 47 | |
| 4aba5fb8 MS |
48 | /* Device Names */ |
| 49 | #define XILINX_XC7Z007S_NAME "7z007s" | |
| 50 | #define XILINX_XC7Z010_NAME "7z010" | |
| 5389564b | 51 | #define XILINX_XC7Z010_LR_NAME "xc7z010_lr" |
| 4aba5fb8 MS |
52 | #define XILINX_XC7Z012S_NAME "7z012s" |
| 53 | #define XILINX_XC7Z014S_NAME "7z014s" | |
| 54 | #define XILINX_XC7Z015_NAME "7z015" | |
| 5389564b | 55 | #define XILINX_XC7Z020_LR_NAME "xa7z020_lr" |
| 4aba5fb8 MS |
56 | #define XILINX_XC7Z020_NAME "7z020" |
| 57 | #define XILINX_XC7Z030_NAME "7z030" | |
| 58 | #define XILINX_XC7Z035_NAME "7z035" | |
| 59 | #define XILINX_XC7Z045_NAME "7z045" | |
| 60 | #define XILINX_XC7Z100_NAME "7z100" | |
| 61 | ||
| 62 | #if defined(CONFIG_FPGA) | |
| 63 | #define ZYNQ_DESC(name) { \ | |
| 64 | .idcode = XILINX_ZYNQ_XC##name, \ | |
| 65 | .fpga_size = XILINX_XC##name##_SIZE, \ | |
| 66 | .devicename = XILINX_XC##name##_NAME \ | |
| 67 | } | |
| 68 | #else | |
| 69 | #define ZYNQ_DESC(name) { \ | |
| 70 | .idcode = XILINX_ZYNQ_XC##name, \ | |
| 71 | .devicename = XILINX_XC##name##_NAME \ | |
| 72 | } | |
| 73 | #endif | |
| fd2b10b6 | 74 | |
| d5dae85f | 75 | #endif /* _ZYNQPL_H_ */ |