projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2118ebb4 SP |
2 | /* |
| 3 | * (C) Copyright 2007-2008 | |
| c9e798d3 | 4 | * Stelian Pop <[email protected]> |
| 2118ebb4 SP |
5 | * Lead Tech Design <www.leadtechdesign.com> |
| 6 | * | |
| 7 | * Configuation settings for the AT91SAM9RLEK board. | |
| 2118ebb4 SP |
8 | */ |
| 9 | ||
| 10 | #ifndef __CONFIG_H | |
| 11 | #define __CONFIG_H | |
| 12 | ||
| 21d671d0 XH |
13 | #include <asm/hardware.h> |
| 14 | ||
| 2118ebb4 | 15 | /* ARM asynchronous clock */ |
| 65cc0e2a TR |
16 | #define CFG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
| 17 | #define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ | |
| 21d671d0 | 18 | |
| 2118ebb4 | 19 | /* SDRAM */ |
| aa6e94de TR |
20 | #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS1 |
| 21 | #define CFG_SYS_SDRAM_SIZE 0x04000000 | |
| 21d671d0 | 22 | |
| 65cc0e2a TR |
23 | #define CFG_SYS_INIT_RAM_SIZE (16 * 1024) |
| 24 | #define CFG_SYS_INIT_RAM_ADDR ATMEL_BASE_SRAM | |
| 2118ebb4 | 25 | |
| 2118ebb4 | 26 | /* NAND flash */ |
| 74c076d6 | 27 | #ifdef CONFIG_CMD_NAND |
| 4e590945 | 28 | #define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 |
| 74c076d6 | 29 | /* our ALE is AD21 */ |
| 4e590945 | 30 | #define CFG_SYS_NAND_MASK_ALE (1 << 21) |
| 74c076d6 | 31 | /* our CLE is AD22 */ |
| 4e590945 TR |
32 | #define CFG_SYS_NAND_MASK_CLE (1 << 22) |
| 33 | #define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6 | |
| 34 | #define CFG_SYS_NAND_READY_PIN AT91_PIN_PD17 | |
| 2eb99ca8 | 35 | |
| 74c076d6 | 36 | #endif |
| 2118ebb4 | 37 | |
| 2118ebb4 | 38 | #endif |