Git Repo - J-u-boot.git/blame - drivers/pinctrl/exynos/pinctrl-exynos78x0.c

Commit	Line	Data
69bde041 DS	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Exynos78x0 pinctrl driver.
	4	*
	5	* Copyright (c) 2020 Dzmitry Sankouski ([email protected])
	6	*
	7	* based on drivers/pinctrl/exynos/pinctrl-exynos7420.c :
	8	* Copyright (C) 2016 Samsung Electronics
	9	* Thomas Abraham <[email protected]>
	10	*/
	11
69bde041 DS	12	#include <dm.h>
	13	#include <errno.h>
	14	#include <asm/io.h>
	15	#include <dm/pinctrl.h>
	16	#include <dm/root.h>
	17	#include <fdtdec.h>
	18	#include <asm/arch/pinmux.h>
	19	#include "pinctrl-exynos.h"
	20
2b77d9a3	21	static const struct pinctrl_ops exynos78x0_pinctrl_ops = {
69bde041 DS	22	.set_state = exynos_pinctrl_set_state
	23	};
	24
	25	/* pin banks of exynos78x0 pin-controller 0 (ALIVE) */
2b77d9a3	26	static const struct samsung_pin_bank_data exynos78x0_pin_banks0[] = {
69bde041 DS	27	EXYNOS_PIN_BANK(6, 0x000, "etc0"),
	28	EXYNOS_PIN_BANK(3, 0x020, "etc1"),
	29	EXYNOS_PIN_BANK(8, 0x040, "gpa0"),
	30	EXYNOS_PIN_BANK(8, 0x060, "gpa1"),
	31	EXYNOS_PIN_BANK(8, 0x080, "gpa2"),
	32	EXYNOS_PIN_BANK(5, 0x0a0, "gpa3"),
	33	EXYNOS_PIN_BANK(2, 0x0c0, "gpq0"),
	34	};
	35
	36	/* pin banks of exynos78x0 pin-controller 1 (CCORE) */
2b77d9a3	37	static const struct samsung_pin_bank_data exynos78x0_pin_banks1[] = {
69bde041 DS	38	EXYNOS_PIN_BANK(2, 0x000, "gpm0"),
	39	};
	40
	41	/* pin banks of exynos78x0 pin-controller 2 (DISPAUD) */
2b77d9a3	42	static const struct samsung_pin_bank_data exynos78x0_pin_banks2[] = {
69bde041 DS	43	EXYNOS_PIN_BANK(4, 0x000, "gpz0"),
	44	EXYNOS_PIN_BANK(6, 0x020, "gpz1"),
	45	EXYNOS_PIN_BANK(4, 0x040, "gpz2"),
	46	};
	47
	48	/* pin banks of exynos78x0 pin-controller 4 (FSYS) */
2b77d9a3	49	static const struct samsung_pin_bank_data exynos78x0_pin_banks4[] = {
69bde041 DS	50	EXYNOS_PIN_BANK(3, 0x000, "gpr0"),
	51	EXYNOS_PIN_BANK(8, 0x020, "gpr1"),
	52	EXYNOS_PIN_BANK(2, 0x040, "gpr2"),
	53	EXYNOS_PIN_BANK(4, 0x060, "gpr3"),
	54	EXYNOS_PIN_BANK(6, 0x080, "gpr4"),
	55	};
	56
	57	/* pin banks of exynos78x0 pin-controller 6 (TOP) */
2b77d9a3	58	static const struct samsung_pin_bank_data exynos78x0_pin_banks6[] = {
69bde041 DS	59	EXYNOS_PIN_BANK(4, 0x000, "gpb0"),
	60	EXYNOS_PIN_BANK(3, 0x020, "gpc0"),
	61	EXYNOS_PIN_BANK(4, 0x040, "gpc1"),
	62	EXYNOS_PIN_BANK(4, 0x060, "gpc4"),
	63	EXYNOS_PIN_BANK(2, 0x080, "gpc5"),
	64	EXYNOS_PIN_BANK(4, 0x0a0, "gpc6"),
	65	EXYNOS_PIN_BANK(2, 0x0c0, "gpc8"),
	66	EXYNOS_PIN_BANK(2, 0x0e0, "gpc9"),
	67	EXYNOS_PIN_BANK(7, 0x100, "gpd1"),
	68	EXYNOS_PIN_BANK(6, 0x120, "gpd2"),
	69	EXYNOS_PIN_BANK(8, 0x140, "gpd3"),
	70	EXYNOS_PIN_BANK(7, 0x160, "gpd4"),
	71	EXYNOS_PIN_BANK(5, 0x180, "gpd5"),
	72	EXYNOS_PIN_BANK(3, 0x1a0, "gpe0"),
	73	EXYNOS_PIN_BANK(4, 0x1c0, "gpf0"),
	74	EXYNOS_PIN_BANK(2, 0x1e0, "gpf1"),
	75	EXYNOS_PIN_BANK(2, 0x200, "gpf2"),
	76	EXYNOS_PIN_BANK(4, 0x220, "gpf3"),
	77	EXYNOS_PIN_BANK(5, 0x240, "gpf4"),
	78	};
	79
2b77d9a3	80	const struct samsung_pin_ctrl exynos78x0_pin_ctrl[] = {
69bde041 DS	81	{
	82	/* pin-controller instance 0 Alive data */
	83	.pin_banks = exynos78x0_pin_banks0,
	84	.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks0),
	85	}, {
	86	/* pin-controller instance 1 CCORE data */
	87	.pin_banks = exynos78x0_pin_banks1,
	88	.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks1),
	89	}, {
	90	/* pin-controller instance 2 DISPAUD data */
	91	.pin_banks = exynos78x0_pin_banks2,
	92	.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks2),
	93	}, {
	94	/* pin-controller instance 4 FSYS data */
	95	.pin_banks = exynos78x0_pin_banks4,
	96	.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks4),
	97	}, {
	98	/* pin-controller instance 6 TOP data */
	99	.pin_banks = exynos78x0_pin_banks6,
	100	.nr_banks = ARRAY_SIZE(exynos78x0_pin_banks6),
	101	},
	102	{/* list terminator */}
	103	};
	104
	105	static const struct udevice_id exynos78x0_pinctrl_ids[] = {
	106	{ .compatible = "samsung,exynos78x0-pinctrl",
	107	.data = (ulong)exynos78x0_pin_ctrl },
	108	{ }
	109	};
	110
	111	U_BOOT_DRIVER(pinctrl_exynos78x0) = {
	112	.name = "pinctrl_exynos78x0",
	113	.id = UCLASS_PINCTRL,
	114	.of_match = exynos78x0_pinctrl_ids,
	115	.priv_auto = sizeof(struct exynos_pinctrl_priv),
	116	.ops = &exynos78x0_pinctrl_ops,
	117	.probe = exynos_pinctrl_probe,
	118	};