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Merge tag 'u-boot-imx-master-20250127' of https://gitlab.denx.de/u-boot/custodians...
[J-u-boot.git] / drivers / mmc / bcmstb_sdhci.c
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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2018 Cisco Systems, Inc.
77934fde 4 * (C) Copyright 2019 Synamedia
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5 *
6 * Author: Thomas Fitzsimmons <[email protected]>
7 */
8
77934fde 9#include <dm.h>
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10#include <mach/sdhci.h>
11#include <malloc.h>
12#include <sdhci.h>
13
14/*
15 * The BCMSTB SDHCI has a quirk in that its actual maximum frequency
16 * capability is 100 MHz. The divisor that is eventually written to
17 * SDHCI_CLOCK_CONTROL is calculated based on what the MMC device
18 * reports, and relative to this maximum frequency.
19 *
20 * This define used to be set to 52000000 (52 MHz), the desired
21 * maximum frequency, but that would result in the communication
22 * actually running at 100 MHz (seemingly without issue), which is
23 * out-of-spec.
24 *
25 * Now, by setting this to 0 (auto-detect), 100 MHz will be read from
26 * the capabilities register, and the resulting divisor will be
27 * doubled, meaning that the clock control register will be set to the
28 * in-spec 52 MHz value.
29 */
30#define BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY 0
31/*
32 * When the minimum clock frequency is set to 0 (auto-detect), U-Boot
33 * sets it to 100 MHz divided by SDHCI_MAX_DIV_SPEC_300, or 48,875 Hz,
34 * which results in the controller timing out when trying to
35 * communicate with the MMC device. Hard-code this value to 400000
36 * (400 kHz) to prevent this.
37 */
38#define BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY 400000
39
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40#define SDIO_CFG_CTRL 0x0
41#define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31)
42#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30)
43
44#define SDIO_CFG_SD_PIN_SEL 0x44
45#define SDIO_CFG_SD_PIN_SEL_MASK 0x3
46#define SDIO_CFG_SD_PIN_SEL_CARD BIT(1)
47
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48struct sdhci_bcmstb_plat {
49 struct mmc_config cfg;
50 struct mmc mmc;
51};
52
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53struct sdhci_brcmstb_dev_priv {
54 int (*init)(struct udevice *dev);
55};
56
57static int sdhci_brcmstb_init_2712(struct udevice *dev)
58{
59 struct sdhci_host *host = dev_get_priv(dev);
60 void *cfg_regs;
61 u32 reg;
62
63 /* Map in the non-standard CFG registers */
64 cfg_regs = dev_remap_addr_name(dev, "cfg");
65 if (!cfg_regs)
66 return -ENOENT;
67
68 if ((host->mmc->host_caps & MMC_CAP_NONREMOVABLE) ||
69 (host->mmc->host_caps & MMC_CAP_NEEDS_POLL)) {
70 /* Force presence */
71 reg = readl(cfg_regs + SDIO_CFG_CTRL);
72 reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV;
73 reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN;
74 writel(reg, cfg_regs + SDIO_CFG_CTRL);
75 } else {
76 /* Enable card detection line */
77 reg = readl(cfg_regs + SDIO_CFG_SD_PIN_SEL);
78 reg &= ~SDIO_CFG_SD_PIN_SEL_MASK;
79 reg |= SDIO_CFG_SD_PIN_SEL_CARD;
80 writel(reg, cfg_regs + SDIO_CFG_SD_PIN_SEL);
81 }
82
83 return 0;
84}
85
77934fde 86static int sdhci_bcmstb_bind(struct udevice *dev)
894c3ad2 87{
c69cda25 88 struct sdhci_bcmstb_plat *plat = dev_get_plat(dev);
894c3ad2 89
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90 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
91}
92
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93/* No specific SDHCI operations are required */
94static const struct sdhci_ops bcmstb_sdhci_ops = { 0 };
95
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96static int sdhci_bcmstb_probe(struct udevice *dev)
97{
98 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
c69cda25 99 struct sdhci_bcmstb_plat *plat = dev_get_plat(dev);
77934fde 100 struct sdhci_host *host = dev_get_priv(dev);
10127cdb 101 struct sdhci_brcmstb_dev_priv *dev_priv;
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102 fdt_addr_t base;
103 int ret;
894c3ad2 104
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105 dev_priv = (struct sdhci_brcmstb_dev_priv *)dev_get_driver_data(dev);
106
2548493a 107 base = dev_read_addr(dev);
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108 if (base == FDT_ADDR_T_NONE)
109 return -EINVAL;
894c3ad2 110
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111 host->name = dev->name;
112 host->ioaddr = (void *)base;
894c3ad2 113
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114 ret = mmc_of_parse(dev, &plat->cfg);
115 if (ret)
116 return ret;
894c3ad2 117
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118 host->mmc = &plat->mmc;
119 host->mmc->dev = dev;
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120 host->ops = &bcmstb_sdhci_ops;
121
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122 ret = sdhci_setup_cfg(&plat->cfg, host,
123 BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
124 BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
125 if (ret)
126 return ret;
127
128 upriv->mmc = &plat->mmc;
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129 host->mmc->priv = host;
130
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131 if (dev_priv && dev_priv->init) {
132 ret = dev_priv->init(dev);
133 if (ret)
134 return ret;
135 }
136
77934fde 137 return sdhci_probe(dev);
894c3ad2 138}
77934fde 139
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140static const struct sdhci_brcmstb_dev_priv match_priv_2712 = {
141 .init = sdhci_brcmstb_init_2712,
142};
143
77934fde 144static const struct udevice_id sdhci_bcmstb_match[] = {
10127cdb 145 { .compatible = "brcm,bcm2712-sdhci", .data = (ulong)&match_priv_2712 },
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146 { .compatible = "brcm,bcm7425-sdhci" },
147 { .compatible = "brcm,sdhci-brcmstb" },
148 { }
149};
150
151U_BOOT_DRIVER(sdhci_bcmstb) = {
152 .name = "sdhci-bcmstb",
153 .id = UCLASS_MMC,
154 .of_match = sdhci_bcmstb_match,
155 .ops = &sdhci_ops,
156 .bind = sdhci_bcmstb_bind,
157 .probe = sdhci_bcmstb_probe,
41575d8e 158 .priv_auto = sizeof(struct sdhci_host),
caa4daa2 159 .plat_auto = sizeof(struct sdhci_bcmstb_plat),
77934fde 160};
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