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Commit | Line | Data |
---|---|---|
0b11dbf7 MY |
1 | # |
2 | # I2C subsystem configuration | |
3 | # | |
4 | ||
59e11ebf SG |
5 | menuconfig I2C |
6 | bool "I2C support" | |
7 | default y | |
8 | help | |
9 | Note: | |
10 | This is a stand-in for an option to enable I2C support. In fact this | |
11 | simply enables building of the I2C directory for U-Boot. The actual | |
12 | I2C feature is enabled by DM_I2C (for driver model) and | |
13 | the #define CONFIG_SYS_I2C_LEGACY (for the legacy I2C stack). | |
14 | ||
15 | So at present there is no need to ever disable this option. | |
16 | ||
17 | Eventually it will: | |
18 | ||
19 | Enable support for the I2C (Inter-Integrated Circuit) bus in U-Boot. | |
20 | I2C works with a clock and data line which can be driven by a | |
21 | one or more masters or slaves. It is a fairly complex bus but is | |
22 | widely used as it only needs two lines for communication. Speeds of | |
23 | 400kbps are typical but up to 3.4Mbps is supported by some | |
24 | hardware. Enable this option to build the drivers in drivers/i2c as | |
25 | part of a U-Boot build. | |
26 | ||
27 | if I2C | |
0b11dbf7 | 28 | |
b6036bcd MY |
29 | config DM_I2C |
30 | bool "Enable Driver Model for I2C drivers" | |
31 | depends on DM | |
32 | help | |
705fcf4d PM |
33 | Enable driver model for I2C. The I2C uclass interface: probe, read, |
34 | write and speed, is implemented with the bus drivers operations, | |
35 | which provide methods for bus setting and data transfer. Each chip | |
caa4daa2 | 36 | device (bus child) info is kept as parent plat. The interface |
e3114824 | 37 | is defined in include/i2c.h. |
4bba9d3f | 38 | |
d1f3abe1 IO |
39 | config SPL_DM_I2C |
40 | bool "Enable Driver Model for I2C drivers in SPL" | |
41 | depends on SPL_DM && DM_I2C | |
42 | default y | |
43 | help | |
44 | Enable driver model for I2C. The I2C uclass interface: probe, read, | |
747093dd SG |
45 | write and speed, is implemented with the bus drivers operations, |
46 | which provide methods for bus setting and data transfer. Each chip | |
47 | device (bus child) info is kept as parent platdata. The interface | |
48 | is defined in include/i2c.h. | |
49 | ||
c7d53f02 SG |
50 | config TPL_DM_I2C |
51 | bool "Enable Driver Model for I2C drivers in TPL" | |
52 | depends on TPL_DM && DM_I2C | |
53 | help | |
54 | Enable driver model for I2C. The I2C uclass interface: probe, read, | |
55 | write and speed, is implemented with the bus drivers operations, | |
56 | which provide methods for bus setting and data transfer. Each chip | |
57 | device (bus child) info is kept as parent platdata. The interface | |
58 | is defined in include/i2c.h. | |
59 | ||
747093dd SG |
60 | config VPL_DM_I2C |
61 | bool "Enable Driver Model for I2C drivers in VPL" | |
62 | depends on VPL_DM && DM_I2C | |
63 | default y | |
64 | help | |
65 | Enable driver model for I2C. The I2C uclass interface: probe, read, | |
d1f3abe1 IO |
66 | write and speed, is implemented with the bus drivers operations, |
67 | which provide methods for bus setting and data transfer. Each chip | |
68 | device (bus child) info is kept as parent platdata. The interface | |
69 | is defined in include/i2c.h. | |
70 | ||
55dabcc8 TR |
71 | config SYS_I2C_LEGACY |
72 | bool "Enable legacy I2C subsystem and drivers" | |
73 | depends on !DM_I2C | |
74 | help | |
75 | Enable the legacy I2C subsystem and drivers. While this is | |
76 | deprecated in U-Boot itself, this can be useful in some situations | |
77 | in SPL or TPL. | |
78 | ||
79 | config SPL_SYS_I2C_LEGACY | |
80 | bool "Enable legacy I2C subsystem and drivers in SPL" | |
81 | depends on SUPPORT_SPL && !SPL_DM_I2C | |
82 | help | |
83 | Enable the legacy I2C subsystem and drivers in SPL. This is useful | |
84 | in some size constrained situations. | |
85 | ||
86 | config TPL_SYS_I2C_LEGACY | |
87 | bool "Enable legacy I2C subsystem and drivers in TPL" | |
88 | depends on SUPPORT_TPL && !SPL_DM_I2C | |
89 | help | |
90 | Enable the legacy I2C subsystem and drivers in TPL. This is useful | |
91 | in some size constrained situations. | |
92 | ||
52c7e375 TR |
93 | config SYS_I2C_EARLY_INIT |
94 | bool "Enable legacy I2C subsystem early in boot" | |
95 | depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC | |
96 | help | |
97 | Add the function prototype for i2c_early_init_f which is called in | |
98 | board_early_init_f. | |
99 | ||
cc456bd7 SG |
100 | config I2C_CROS_EC_TUNNEL |
101 | tristate "Chrome OS EC tunnel I2C bus" | |
102 | depends on CROS_EC | |
103 | help | |
104 | This provides an I2C bus that will tunnel i2c commands through to | |
105 | the other side of the Chrome OS EC to the I2C bus connected there. | |
106 | This will work whatever the interface used to talk to the EC (SPI, | |
107 | I2C or LPC). Some Chromebooks use this when the hardware design | |
108 | does not allow direct access to the main PMIC from the AP. | |
109 | ||
f48eaf01 SG |
110 | config I2C_CROS_EC_LDO |
111 | bool "Provide access to LDOs on the Chrome OS EC" | |
112 | depends on CROS_EC | |
113 | ---help--- | |
114 | On many Chromebooks the main PMIC is inaccessible to the AP. This is | |
115 | often dealt with by using an I2C pass-through interface provided by | |
116 | the EC. On some unfortunate models (e.g. Spring) the pass-through | |
117 | is not available, and an LDO message is available instead. This | |
118 | option enables a driver which provides very basic access to those | |
119 | regulators, via the EC. We implement this as an I2C bus which | |
120 | emulates just the TPS65090 messages we know about. This is done to | |
121 | avoid duplicating the logic in the TPS65090 regulator driver for | |
122 | enabling/disabling an LDO. | |
cc456bd7 | 123 | |
e46f8a33 LM |
124 | config I2C_SET_DEFAULT_BUS_NUM |
125 | bool "Set default I2C bus number" | |
126 | depends on DM_I2C | |
127 | help | |
128 | Set default number of I2C bus to be accessed. This option provides | |
129 | behaviour similar to old (i.e. pre DM) I2C bus driver. | |
130 | ||
131 | config I2C_DEFAULT_BUS_NUMBER | |
132 | hex "I2C default bus number" | |
133 | depends on I2C_SET_DEFAULT_BUS_NUM | |
134 | default 0x0 | |
135 | help | |
136 | Number of default I2C bus to use | |
137 | ||
c54473cb PM |
138 | config DM_I2C_GPIO |
139 | bool "Enable Driver Model for software emulated I2C bus driver" | |
140 | depends on DM_I2C && DM_GPIO | |
141 | help | |
142 | Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO | |
143 | configuration is given by the device tree. Kernel-style device tree | |
144 | bindings are supported. | |
145 | Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt | |
146 | ||
d1f3abe1 IO |
147 | config SPL_DM_I2C_GPIO |
148 | bool "Enable Driver Model for software emulated I2C bus driver in SPL" | |
83061dbd | 149 | depends on SPL_DM && DM_I2C_GPIO && SPL_DM_GPIO && SPL_GPIO |
d1f3abe1 IO |
150 | default y |
151 | help | |
152 | Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO | |
153 | configuration is given by the device tree. Kernel-style device tree | |
154 | bindings are supported. | |
155 | Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt | |
156 | ||
8800e0fa SW |
157 | config SYS_I2C_AT91 |
158 | bool "Atmel I2C driver" | |
159 | depends on DM_I2C && ARCH_AT91 | |
160 | help | |
161 | Add support for the Atmel I2C driver. A serious problem is that there | |
162 | is no documented way to issue repeated START conditions for more than | |
163 | two messages, as needed to support combined I2C messages. Use the | |
164 | i2c-gpio driver unless your system can cope with this limitation. | |
165 | Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt | |
166 | ||
956d57a8 RK |
167 | config SYS_I2C_IPROC |
168 | bool "Broadcom I2C driver" | |
169 | depends on DM_I2C | |
170 | help | |
171 | Broadcom I2C driver. | |
172 | Add support for Broadcom I2C driver. | |
173 | Say yes here to to enable the Broadco I2C driver. | |
174 | ||
dbc82ce3 | 175 | config SYS_I2C_FSL |
176 | bool "Freescale I2C bus driver" | |
dbc82ce3 | 177 | help |
178 | Add support for Freescale I2C busses as used on MPC8240, MPC8245, and | |
179 | MPC85xx processors. | |
180 | ||
6d5d0c95 TR |
181 | if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) |
182 | config SYS_FSL_I2C_OFFSET | |
183 | hex "Offset from the IMMR of the address of the first I2C controller" | |
184 | ||
185 | config SYS_FSL_HAS_I2C2_OFFSET | |
186 | bool "Support a second I2C controller" | |
187 | ||
188 | config SYS_FSL_I2C2_OFFSET | |
189 | hex "Offset from the IMMR of the address of the second I2C controller" | |
190 | depends on SYS_FSL_HAS_I2C2_OFFSET | |
191 | ||
192 | config SYS_FSL_HAS_I2C3_OFFSET | |
193 | bool "Support a third I2C controller" | |
194 | ||
195 | config SYS_FSL_I2C3_OFFSET | |
196 | hex "Offset from the IMMR of the address of the third I2C controller" | |
197 | depends on SYS_FSL_HAS_I2C3_OFFSET | |
198 | ||
199 | config SYS_FSL_HAS_I2C4_OFFSET | |
200 | bool "Support a fourth I2C controller" | |
201 | ||
202 | config SYS_FSL_I2C4_OFFSET | |
203 | hex "Offset from the IMMR of the address of the fourth I2C controller" | |
204 | depends on SYS_FSL_HAS_I2C4_OFFSET | |
205 | endif | |
206 | ||
fdec2d21 MF |
207 | config SYS_I2C_CADENCE |
208 | tristate "Cadence I2C Controller" | |
664e16ce | 209 | depends on DM_I2C |
fdec2d21 MF |
210 | help |
211 | Say yes here to select Cadence I2C Host Controller. This controller is | |
212 | e.g. used by Xilinx Zynq. | |
213 | ||
7f5ea250 AL |
214 | config SYS_I2C_CA |
215 | tristate "Cortina-Access I2C Controller" | |
216 | depends on DM_I2C && CORTINA_PLATFORM | |
7f5ea250 AL |
217 | help |
218 | Add support for the Cortina Access I2C host controller. | |
219 | Say yes here to select Cortina-Access I2C Host Controller. | |
220 | ||
9f8cf76b AF |
221 | config SYS_I2C_DAVINCI |
222 | bool "Davinci I2C Controller" | |
223 | depends on (ARCH_KEYSTONE || ARCH_DAVINCI) | |
224 | help | |
225 | Say yes here to add support for Davinci and Keystone I2C controller | |
226 | ||
e32d0db7 SR |
227 | config SYS_I2C_DW |
228 | bool "Designware I2C Controller" | |
e32d0db7 SR |
229 | help |
230 | Say yes here to select the Designware I2C Host Controller. This | |
231 | controller is used in various SoCs, e.g. the ST SPEAr, Altera | |
232 | SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs. | |
233 | ||
7eb62cb7 MC |
234 | config SYS_I2C_DW_PCI |
235 | bool "Designware PCI I2C Controller" | |
236 | depends on SYS_I2C_DW && PCI && ACPIGEN | |
237 | default y | |
238 | help | |
239 | Say yes here to select the Designware PCI I2C Host Controller. | |
240 | This PCI I2C controller is the base on Desigware I2C host | |
241 | controller. | |
242 | ||
4088f5fc RC |
243 | config SYS_I2C_AST2600 |
244 | bool "AST2600 I2C Controller" | |
245 | depends on DM_I2C && ARCH_ASPEED | |
246 | help | |
247 | Say yes here to select AST2600 I2C Host Controller. The driver | |
248 | support AST2600 I2C new mode register. This I2C controller supports: | |
249 | _Standard-mode (up to 100 kHz) | |
250 | _Fast-mode (up to 400 kHz) | |
251 | _Fast-mode Plus (up to 1 MHz) | |
252 | ||
4dc038f3 | 253 | config SYS_I2C_ASPEED |
254 | bool "Aspeed I2C Controller" | |
255 | depends on DM_I2C && ARCH_ASPEED | |
256 | help | |
257 | Say yes here to select Aspeed I2C Host Controller. The driver | |
258 | supports AST2500 and AST2400 controllers, but is very limited. | |
259 | Only single master mode is supported and only byte-by-byte | |
260 | synchronous reads and writes are supported, no Pool Buffers or DMA. | |
261 | ||
abb0b01e SG |
262 | config SYS_I2C_INTEL |
263 | bool "Intel I2C/SMBUS driver" | |
264 | depends on DM_I2C | |
265 | help | |
266 | Add support for the Intel SMBUS driver. So far this driver is just | |
267 | a stub which perhaps some basic init. There is no implementation of | |
268 | the I2C API meaning that any I2C operations will immediately fail | |
269 | for now. | |
270 | ||
7ee3f149 PF |
271 | config SYS_I2C_IMX_LPI2C |
272 | bool "NXP i.MX LPI2C driver" | |
7ee3f149 PF |
273 | help |
274 | Add support for the NXP i.MX LPI2C driver. | |
275 | ||
0705556b TW |
276 | config SYS_I2C_LPC32XX |
277 | bool "LPC32XX I2C driver" | |
278 | depends on ARCH_LPC32XX | |
279 | help | |
280 | Enable support for the LPC32xx I2C driver. | |
281 | ||
f8d9ca18 BG |
282 | config SYS_I2C_MESON |
283 | bool "Amlogic Meson I2C driver" | |
284 | depends on DM_I2C && ARCH_MESON | |
285 | help | |
4ecbb8b6 BG |
286 | Add support for the I2C controller available in Amlogic Meson |
287 | SoCs. The controller supports programmable bus speed including | |
288 | standard (100kbits/s) and fast (400kbit/s) speed and allows the | |
289 | software to define a flexible format of the bit streams. It has an | |
290 | internal buffer holding up to 8 bytes for transfers and supports | |
291 | both 7-bit and 10-bit addresses. | |
f8d9ca18 | 292 | |
9ad71f63 WG |
293 | config SYS_I2C_MTK |
294 | bool "MediaTek I2C driver" | |
295 | help | |
296 | This selects the MediaTek Integrated Inter Circuit bus driver. | |
297 | The I2C bus adapter is the base for some other I2C client, | |
298 | eg: touch, sensors. | |
299 | If you want to use MediaTek I2C interface, say Y here. | |
300 | If unsure, say N. | |
301 | ||
0dc0d1e0 PB |
302 | config SYS_I2C_MICROCHIP |
303 | bool "Microchip I2C driver" | |
304 | help | |
305 | Add support for the Microchip I2C driver. This is operating on | |
306 | standard mode up to 100 kbits/s and fast mode up to 400 kbits/s. | |
307 | ||
72c8c10b | 308 | config SYS_I2C_MXC |
942ecc8b | 309 | bool "NXP MXC I2C driver" |
72c8c10b | 310 | help |
74751454 CP |
311 | Add support for the NXP I2C driver. This supports up to four bus |
312 | channels and operating on standard mode up to 100 kbits/s and fast | |
313 | mode up to 400 kbits/s. | |
72c8c10b | 314 | |
15e7b768 | 315 | if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) |
942ecc8b SD |
316 | config SYS_I2C_MXC_I2C1 |
317 | bool "NXP MXC I2C1" | |
318 | help | |
319 | Add support for NXP MXC I2C Controller 1. | |
320 | Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A | |
321 | ||
322 | config SYS_I2C_MXC_I2C2 | |
323 | bool "NXP MXC I2C2" | |
324 | help | |
325 | Add support for NXP MXC I2C Controller 2. | |
326 | Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A | |
327 | ||
328 | config SYS_I2C_MXC_I2C3 | |
329 | bool "NXP MXC I2C3" | |
330 | help | |
331 | Add support for NXP MXC I2C Controller 3. | |
332 | Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A | |
333 | ||
334 | config SYS_I2C_MXC_I2C4 | |
335 | bool "NXP MXC I2C4" | |
336 | help | |
337 | Add support for NXP MXC I2C Controller 4. | |
338 | Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A | |
fa452192 SD |
339 | |
340 | config SYS_I2C_MXC_I2C5 | |
341 | bool "NXP MXC I2C5" | |
342 | help | |
343 | Add support for NXP MXC I2C Controller 5. | |
344 | Required for SoCs which have I2C MXC controller 5 eg LX2160A | |
345 | ||
346 | config SYS_I2C_MXC_I2C6 | |
347 | bool "NXP MXC I2C6" | |
348 | help | |
349 | Add support for NXP MXC I2C Controller 6. | |
350 | Required for SoCs which have I2C MXC controller 6 eg LX2160A | |
351 | ||
352 | config SYS_I2C_MXC_I2C7 | |
353 | bool "NXP MXC I2C7" | |
354 | help | |
355 | Add support for NXP MXC I2C Controller 7. | |
356 | Required for SoCs which have I2C MXC controller 7 eg LX2160A | |
357 | ||
358 | config SYS_I2C_MXC_I2C8 | |
359 | bool "NXP MXC I2C8" | |
360 | help | |
361 | Add support for NXP MXC I2C Controller 8. | |
362 | Required for SoCs which have I2C MXC controller 8 eg LX2160A | |
942ecc8b SD |
363 | endif |
364 | ||
365 | if SYS_I2C_MXC_I2C1 | |
366 | config SYS_MXC_I2C1_SPEED | |
367 | int "I2C Channel 1 speed" | |
2ce7b65d | 368 | default 40000000 if TARGET_LS2080A_EMU |
942ecc8b SD |
369 | default 100000 |
370 | help | |
371 | MXC I2C Channel 1 speed | |
372 | ||
373 | config SYS_MXC_I2C1_SLAVE | |
15e7b768 | 374 | hex "I2C1 Slave" |
a077ac13 | 375 | default 0x0 |
942ecc8b SD |
376 | help |
377 | MXC I2C1 Slave | |
378 | endif | |
379 | ||
380 | if SYS_I2C_MXC_I2C2 | |
381 | config SYS_MXC_I2C2_SPEED | |
382 | int "I2C Channel 2 speed" | |
2ce7b65d | 383 | default 40000000 if TARGET_LS2080A_EMU |
942ecc8b SD |
384 | default 100000 |
385 | help | |
386 | MXC I2C Channel 2 speed | |
387 | ||
388 | config SYS_MXC_I2C2_SLAVE | |
15e7b768 | 389 | hex "I2C2 Slave" |
a077ac13 | 390 | default 0x0 |
942ecc8b SD |
391 | help |
392 | MXC I2C2 Slave | |
393 | endif | |
394 | ||
395 | if SYS_I2C_MXC_I2C3 | |
396 | config SYS_MXC_I2C3_SPEED | |
397 | int "I2C Channel 3 speed" | |
398 | default 100000 | |
399 | help | |
400 | MXC I2C Channel 3 speed | |
401 | ||
402 | config SYS_MXC_I2C3_SLAVE | |
15e7b768 | 403 | hex "I2C3 Slave" |
a077ac13 | 404 | default 0x0 |
942ecc8b SD |
405 | help |
406 | MXC I2C3 Slave | |
407 | endif | |
408 | ||
409 | if SYS_I2C_MXC_I2C4 | |
410 | config SYS_MXC_I2C4_SPEED | |
411 | int "I2C Channel 4 speed" | |
412 | default 100000 | |
413 | help | |
414 | MXC I2C Channel 4 speed | |
415 | ||
416 | config SYS_MXC_I2C4_SLAVE | |
15e7b768 | 417 | hex "I2C4 Slave" |
a077ac13 | 418 | default 0x0 |
942ecc8b SD |
419 | help |
420 | MXC I2C4 Slave | |
421 | endif | |
422 | ||
fa452192 SD |
423 | if SYS_I2C_MXC_I2C5 |
424 | config SYS_MXC_I2C5_SPEED | |
425 | int "I2C Channel 5 speed" | |
426 | default 100000 | |
427 | help | |
428 | MXC I2C Channel 5 speed | |
429 | ||
430 | config SYS_MXC_I2C5_SLAVE | |
15e7b768 | 431 | hex "I2C5 Slave" |
a077ac13 | 432 | default 0x0 |
fa452192 SD |
433 | help |
434 | MXC I2C5 Slave | |
435 | endif | |
436 | ||
437 | if SYS_I2C_MXC_I2C6 | |
438 | config SYS_MXC_I2C6_SPEED | |
439 | int "I2C Channel 6 speed" | |
440 | default 100000 | |
441 | help | |
442 | MXC I2C Channel 6 speed | |
443 | ||
444 | config SYS_MXC_I2C6_SLAVE | |
15e7b768 | 445 | hex "I2C6 Slave" |
a077ac13 | 446 | default 0x0 |
fa452192 SD |
447 | help |
448 | MXC I2C6 Slave | |
449 | endif | |
450 | ||
451 | if SYS_I2C_MXC_I2C7 | |
452 | config SYS_MXC_I2C7_SPEED | |
453 | int "I2C Channel 7 speed" | |
454 | default 100000 | |
455 | help | |
456 | MXC I2C Channel 7 speed | |
457 | ||
458 | config SYS_MXC_I2C7_SLAVE | |
15e7b768 | 459 | hex "I2C7 Slave" |
a077ac13 | 460 | default 0x0 |
fa452192 SD |
461 | help |
462 | MXC I2C7 Slave | |
463 | endif | |
464 | ||
465 | if SYS_I2C_MXC_I2C8 | |
466 | config SYS_MXC_I2C8_SPEED | |
467 | int "I2C Channel 8 speed" | |
468 | default 100000 | |
469 | help | |
470 | MXC I2C Channel 8 speed | |
471 | ||
472 | config SYS_MXC_I2C8_SLAVE | |
15e7b768 | 473 | hex "I2C8 Slave" |
a077ac13 | 474 | default 0x0 |
fa452192 SD |
475 | help |
476 | MXC I2C8 Slave | |
477 | endif | |
478 | ||
c25e9e04 SB |
479 | config SYS_I2C_NEXELL |
480 | bool "Nexell I2C driver" | |
481 | depends on DM_I2C | |
482 | help | |
483 | Add support for the Nexell I2C driver. This is used with various | |
484 | Nexell parts such as S5Pxx18 series SoCs. All chips | |
485 | have several I2C ports and all are provided, controlled by the | |
486 | device tree. | |
487 | ||
2b77eea7 JL |
488 | config SYS_I2C_NPCM |
489 | bool "Nuvoton NPCM I2C driver" | |
490 | help | |
491 | Support for Nuvoton I2C controller driver. | |
492 | ||
b2d4cbe6 PP |
493 | config SYS_I2C_OCORES |
494 | bool "ocores I2C driver" | |
495 | depends on DM_I2C | |
496 | help | |
497 | Add support for ocores I2C controller. For details see | |
498 | https://opencores.org/projects/i2c | |
499 | ||
daa0f050 AF |
500 | config SYS_I2C_OMAP24XX |
501 | bool "TI OMAP2+ I2C driver" | |
14106bca | 502 | depends on ARCH_OMAP2PLUS || ARCH_K3 |
daa0f050 AF |
503 | help |
504 | Add support for the OMAP2+ I2C driver. | |
505 | ||
a06a0ac3 | 506 | config SYS_I2C_RCAR_I2C |
1fea5781 | 507 | bool "Renesas R-Car I2C driver" |
79da1a96 | 508 | depends on (RCAR_GEN2 || RCAR_64) && DM_I2C |
a06a0ac3 | 509 | help |
1fea5781 | 510 | Support for Renesas R-Car I2C controller. |
a06a0ac3 | 511 | |
9e75ea46 | 512 | config SYS_I2C_RCAR_IIC |
1fea5781 | 513 | bool "Renesas R-Car Gen3 IIC driver" |
61eb551f | 514 | depends on (RCAR_GEN2 || RCAR_GEN3) && DM_I2C |
9e75ea46 | 515 | help |
1fea5781 | 516 | Support for Renesas R-Car Gen3 IIC controller. |
9e75ea46 | 517 | |
34374699 SG |
518 | config SYS_I2C_ROCKCHIP |
519 | bool "Rockchip I2C driver" | |
520 | depends on DM_I2C | |
521 | help | |
522 | Add support for the Rockchip I2C driver. This is used with various | |
523 | Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips | |
74751454 | 524 | have several I2C ports and all are provided, controlled by the |
34374699 SG |
525 | device tree. |
526 | ||
266e36f7 PB |
527 | config SYS_I2C_RZ_RIIC |
528 | bool "Renesas RZ/G2L RIIC driver" | |
529 | depends on RZG2L && DM_I2C | |
530 | help | |
531 | Support for the I2C controller (RIIC) on the Renesas RZ/G2L SoC | |
532 | family. | |
533 | ||
1174aada SG |
534 | config SYS_I2C_SANDBOX |
535 | bool "Sandbox I2C driver" | |
536 | depends on SANDBOX && DM_I2C | |
c7d53f02 SG |
537 | default y |
538 | help | |
539 | Enable I2C support for sandbox. This is an emulation of a real I2C | |
540 | bus. Devices can be attached to the bus using the device tree | |
541 | which specifies the driver to use. See sandbox.dts as an example. | |
542 | ||
543 | config SPL_SYS_I2C_SANDBOX | |
544 | bool "Sandbox I2C driver (SPL)" | |
545 | depends on SPL && SANDBOX && DM_I2C | |
546 | default y | |
1174aada SG |
547 | help |
548 | Enable I2C support for sandbox. This is an emulation of a real I2C | |
549 | bus. Devices can be attached to the bus using the device tree | |
c77c7db5 | 550 | which specifies the driver to use. See sandbox.dts as an example. |
1174aada | 551 | |
6aa07543 TR |
552 | config SYS_I2C_SH |
553 | bool "Legacy SuperH I2C interface" | |
f9aabd45 | 554 | depends on ARCH_RENESAS && SYS_I2C_LEGACY |
6aa07543 TR |
555 | help |
556 | Enable the legacy SuperH I2C interface. | |
557 | ||
558 | if SYS_I2C_SH | |
559 | config SYS_I2C_SH_NUM_CONTROLLERS | |
560 | int | |
561 | default 5 | |
562 | ||
563 | config SYS_I2C_SH_BASE0 | |
564 | hex | |
565 | default 0xE6820000 | |
566 | ||
567 | config SYS_I2C_SH_BASE1 | |
568 | hex | |
569 | default 0xE6822000 | |
570 | ||
571 | config SYS_I2C_SH_BASE2 | |
572 | hex | |
573 | default 0xE6824000 | |
574 | ||
575 | config SYS_I2C_SH_BASE3 | |
576 | hex | |
577 | default 0xE6826000 | |
578 | ||
579 | config SYS_I2C_SH_BASE4 | |
580 | hex | |
581 | default 0xE6828000 | |
582 | ||
583 | config SH_I2C_8BIT | |
584 | bool | |
585 | default y | |
586 | ||
587 | config SH_I2C_DATA_HIGH | |
588 | int | |
589 | default 4 | |
590 | ||
591 | config SH_I2C_DATA_LOW | |
592 | int | |
593 | default 5 | |
594 | ||
595 | config SH_I2C_CLOCK | |
596 | int | |
597 | default 104000000 | |
598 | endif | |
599 | ||
de695725 TR |
600 | config SYS_I2C_SOFT |
601 | bool "Legacy software I2C interface" | |
602 | help | |
603 | Enable the legacy software defined I2C interface | |
604 | ||
605 | config SYS_I2C_SOFT_SPEED | |
606 | int "Software I2C bus speed" | |
607 | depends on SYS_I2C_SOFT | |
608 | default 100000 | |
609 | help | |
610 | Speed of the software I2C bus | |
611 | ||
612 | config SYS_I2C_SOFT_SLAVE | |
613 | hex "Software I2C slave address" | |
614 | depends on SYS_I2C_SOFT | |
615 | default 0xfe | |
616 | help | |
617 | Slave address of the software I2C bus | |
618 | ||
5c2c3e8b SG |
619 | config SYS_I2C_OCTEON |
620 | bool "Octeon II/III/TX/TX2 I2C driver" | |
621 | depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C | |
622 | default y | |
623 | help | |
624 | Add support for the Marvell Octeon I2C driver. This is used with | |
625 | various Octeon parts such as Octeon II/III and OcteonTX/TX2. All | |
626 | chips have several I2C ports and all are provided, controlled by | |
627 | the device tree. | |
628 | ||
9bdec960 SG |
629 | config SYS_I2C_QUP |
630 | bool "Qualcomm QUP I2C controller" | |
631 | depends on ARCH_SNAPDRAGON | |
632 | help | |
633 | Support for Qualcomm QUP I2C controller based on Qualcomm Universal | |
634 | Peripherals (QUP) engine. The QUP engine is an advanced high | |
635 | performance slave port that provides a common data path (an output | |
636 | FIFO and an input FIFO) for I2C and SPI interfaces. The I2C/SPI QUP | |
637 | controller is publicly documented in the Snapdragon 410E (APQ8016E) | |
638 | Technical Reference Manual, chapter "6.1 Qualcomm Universal | |
639 | Peripherals Engine (QUP)". | |
640 | ||
75db9ede NA |
641 | config SYS_I2C_GENI |
642 | bool "Qualcomm Generic Interface (GENI) I2C controller" | |
643 | depends on ARCH_SNAPDRAGON | |
644 | help | |
645 | Support for the Qualcomm Generic Interface (GENI) I2C interface. | |
646 | The Generic Interface (GENI) is a firmware based Qualcomm Universal | |
647 | Peripherals (QUP) Serial Engine (SE) Wrapper which can support multiple | |
648 | bus protocols depending on the firmware type loaded at early boot time | |
649 | based on system configuration. | |
650 | ||
1d61ad95 JC |
651 | config SYS_I2C_S3C24X0 |
652 | bool "Samsung I2C driver" | |
101f4e66 | 653 | depends on DM_I2C |
1d61ad95 JC |
654 | help |
655 | Support for Samsung I2C controller as Samsung SoCs. | |
1174aada | 656 | |
4fadcaf0 PC |
657 | config SYS_I2C_STM32F7 |
658 | bool "STMicroelectronics STM32F7 I2C support" | |
2514c2d0 | 659 | depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C |
4fadcaf0 PC |
660 | help |
661 | Enable this option to add support for STM32 I2C controller | |
662 | introduced with STM32F7/H7 SoCs. This I2C controller supports : | |
663 | _ Slave and master modes | |
664 | _ Multimaster capability | |
665 | _ Standard-mode (up to 100 kHz) | |
666 | _ Fast-mode (up to 400 kHz) | |
667 | _ Fast-mode Plus (up to 1 MHz) | |
668 | _ 7-bit and 10-bit addressing mode | |
669 | _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) | |
670 | _ All 7-bit addresses acknowledge mode | |
671 | _ General call | |
672 | _ Programmable setup and hold times | |
673 | _ Easy to use event management | |
674 | _ Optional clock stretching | |
675 | _ Software reset | |
676 | ||
104950a7 SH |
677 | config SYS_I2C_SUN6I_P2WI |
678 | bool "Allwinner sun6i P2WI controller" | |
679 | depends on ARCH_SUNXI | |
680 | help | |
681 | Support for the P2WI (Push/Pull 2 Wire Interface) controller embedded | |
682 | in the Allwinner A31 and A31s SOCs. This interface is used to connect | |
683 | to specific devices like the X-Powers AXP221 PMIC. | |
684 | ||
3227c85f SH |
685 | config SYS_I2C_SUN8I_RSB |
686 | bool "Allwinner sun8i Reduced Serial Bus controller" | |
687 | depends on ARCH_SUNXI | |
688 | help | |
689 | Support for Allwinner's Reduced Serial Bus (RSB) controller. This | |
690 | controller is responsible for communicating with various RSB based | |
691 | devices, such as X-Powers AXPxxx PMICs and AC100/AC200 CODEC ICs. | |
692 | ||
4483fbab JB |
693 | config SYS_I2C_SYNQUACER |
694 | bool "Socionext SynQuacer I2C controller" | |
695 | depends on ARCH_SYNQUACER && DM_I2C | |
696 | help | |
697 | Support for Socionext Synquacer I2C controller. This I2C controller | |
698 | will be used for RTC and LS-connector on DeveloperBox. | |
699 | ||
02253d4d PR |
700 | config SYS_I2C_TEGRA |
701 | bool "NVIDIA Tegra internal I2C controller" | |
18138ab2 | 702 | depends on ARCH_TEGRA |
02253d4d PR |
703 | help |
704 | Support for NVIDIA I2C controller available in Tegra SoCs. | |
705 | ||
26f820f3 MY |
706 | config SYS_I2C_UNIPHIER |
707 | bool "UniPhier I2C driver" | |
708 | depends on ARCH_UNIPHIER && DM_I2C | |
709 | default y | |
710 | help | |
b6ef3a3f MY |
711 | Support for UniPhier I2C controller driver. This I2C controller |
712 | is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. | |
238bd0b8 MY |
713 | |
714 | config SYS_I2C_UNIPHIER_F | |
715 | bool "UniPhier FIFO-builtin I2C driver" | |
716 | depends on ARCH_UNIPHIER && DM_I2C | |
717 | default y | |
718 | help | |
b6ef3a3f | 719 | Support for UniPhier FIFO-builtin I2C controller driver. |
238bd0b8 | 720 | This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. |
3d1957f0 | 721 | |
e3bc4bb8 HS |
722 | config SYS_I2C_VERSATILE |
723 | bool "Arm Ltd Versatile I2C bus driver" | |
c6c26a05 | 724 | depends on DM_I2C && TARGET_VEXPRESS64_JUNO |
e3bc4bb8 HS |
725 | help |
726 | Add support for the Arm Ltd Versatile Express I2C driver. The I2C host | |
727 | controller is present in the development boards manufactured by Arm Ltd. | |
728 | ||
999ac22b MB |
729 | config SYS_I2C_MV |
730 | bool "Marvell PXA (Armada 3720) I2C driver" | |
731 | help | |
732 | Support for PXA based I2C controller used on Armada 3720 SoC. | |
733 | In Linux, this driver is called i2c-pxa. | |
734 | ||
14a6ff2c | 735 | config SYS_I2C_MVTWSI |
736 | bool "Marvell I2C driver" | |
14a6ff2c | 737 | help |
738 | Support for Marvell I2C controllers as used on the orion5x and | |
739 | kirkwood SoC families. | |
740 | ||
34f1c9fe SW |
741 | config TEGRA186_BPMP_I2C |
742 | bool "Enable Tegra186 BPMP-based I2C driver" | |
743 | depends on TEGRA186_BPMP | |
744 | help | |
745 | Support for Tegra I2C controllers managed by the BPMP (Boot and | |
746 | Power Management Processor). On Tegra186, some I2C controllers are | |
747 | directly controlled by the main CPU, whereas others are controlled | |
748 | by the BPMP, and can only be accessed by the main CPU via IPC | |
749 | requests to the BPMP. This driver covers the latter case. | |
750 | ||
a5752f8a TR |
751 | config SYS_I2C_SLAVE |
752 | hex "I2C Slave address channel (all buses)" | |
753 | depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY | |
754 | default 0xfe | |
755 | help | |
756 | I2C Slave address channel 0 for all buses in the legacy drivers. | |
757 | Many boards/controllers/drivers don't support an I2C slave | |
758 | interface so provide a default slave address for them for use in | |
759 | common code. A real value for CONFIG_SYS_I2C_SLAVE should be | |
760 | defined for any board which does support a slave interface and | |
761 | this default used otherwise. | |
762 | ||
763 | config SYS_I2C_SPEED | |
764 | int "I2C Slave channel 0 speed (all buses)" | |
765 | depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY | |
766 | default 100000 | |
767 | help | |
768 | I2C Slave speed channel 0 for all buses in the legacy drivers. | |
769 | ||
fc760cc6 AF |
770 | config SYS_I2C_BUS_MAX |
771 | int "Max I2C busses" | |
cb42c1f9 | 772 | depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA |
cb42c1f9 | 773 | default 3 if OMAP34XX || AM33XX || AM43XX |
b0ee3fe6 | 774 | default 4 if ARCH_SOCFPGA |
fc760cc6 AF |
775 | default 5 if OMAP54XX |
776 | help | |
777 | Define the maximum number of available I2C buses. | |
778 | ||
ad827a50 MV |
779 | config SYS_I2C_XILINX_XIIC |
780 | bool "Xilinx AXI I2C driver" | |
781 | depends on DM_I2C | |
782 | help | |
783 | Support for Xilinx AXI I2C controller. | |
784 | ||
92164216 MS |
785 | config SYS_I2C_IHS |
786 | bool "gdsys IHS I2C driver" | |
787 | depends on DM_I2C | |
788 | help | |
789 | Support for gdsys IHS I2C driver on FPGA bus. | |
790 | ||
3d1957f0 | 791 | source "drivers/i2c/muxes/Kconfig" |
0b11dbf7 | 792 | |
59e11ebf | 793 | endif |