[J-u-boot.git] / drivers / mmc / fsl_esdhc.c

/*
 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
 * Andy Fleming
 *
 * Based vaguely on the pxa mmc code:
 * (C) Copyright 2003
 * Kyle Harris, Nexus Technologies, Inc. [email protected]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <command.h>
#include <hwconfig.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <fdt_support.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

struct fsl_esdhc {
	uint	dsaddr;
	uint	blkattr;
	uint	cmdarg;
	uint	xfertyp;
	uint	cmdrsp0;
	uint	cmdrsp1;
	uint	cmdrsp2;
	uint	cmdrsp3;
	uint	datport;
	uint	prsstat;
	uint	proctl;
	uint	sysctl;
	uint	irqstat;
	uint	irqstaten;
	uint	irqsigen;
	uint	autoc12err;
	uint	hostcapblt;
	uint	wml;
	uint    mixctrl;
	char    reserved1[4];
	uint	fevt;
	char	reserved2[168];
	uint	hostver;
	char	reserved3[780];
	uint	scr;
};

/* Return the XFERTYP flags for a given command and data packet */
uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
{
	uint xfertyp = 0;

	if (data) {
		xfertyp |= XFERTYP_DPSEL;
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
		xfertyp |= XFERTYP_DMAEN;
#endif
		if (data->blocks > 1) {
			xfertyp |= XFERTYP_MSBSEL;
			xfertyp |= XFERTYP_BCEN;
#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
			xfertyp |= XFERTYP_AC12EN;
#endif
		}

		if (data->flags & MMC_DATA_READ)
			xfertyp |= XFERTYP_DTDSEL;
	}

	if (cmd->resp_type & MMC_RSP_CRC)
		xfertyp |= XFERTYP_CCCEN;
	if (cmd->resp_type & MMC_RSP_OPCODE)
		xfertyp |= XFERTYP_CICEN;
	if (cmd->resp_type & MMC_RSP_136)
		xfertyp |= XFERTYP_RSPTYP_136;
	else if (cmd->resp_type & MMC_RSP_BUSY)
		xfertyp |= XFERTYP_RSPTYP_48_BUSY;
	else if (cmd->resp_type & MMC_RSP_PRESENT)
		xfertyp |= XFERTYP_RSPTYP_48;

#ifdef CONFIG_MX53
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		xfertyp |= XFERTYP_CMDTYP_ABORT;
#endif
	return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
}

#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
/*
 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
 */
static void
esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
{
	struct fsl_esdhc_cfg *cfg = mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	uint blocks;
	char *buffer;
	uint databuf;
	uint size;
	uint irqstat;
	uint timeout;

	if (data->flags & MMC_DATA_READ) {
		blocks = data->blocks;
		buffer = data->dest;
		while (blocks) {
			timeout = PIO_TIMEOUT;
			size = data->blocksize;
			irqstat = esdhc_read32(&regs->irqstat);
			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
				&& --timeout);
			if (timeout <= 0) {
				printf("\nData Read Failed in PIO Mode.");
				return;
			}
			while (size && (!(irqstat & IRQSTAT_TC))) {
				udelay(100); /* Wait before last byte transfer complete */
				irqstat = esdhc_read32(&regs->irqstat);
				databuf = in_le32(&regs->datport);
				*((uint *)buffer) = databuf;
				buffer += 4;
				size -= 4;
			}
			blocks--;
		}
	} else {
		blocks = data->blocks;
		buffer = (char *)data->src;
		while (blocks) {
			timeout = PIO_TIMEOUT;
			size = data->blocksize;
			irqstat = esdhc_read32(&regs->irqstat);
			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
				&& --timeout);
			if (timeout <= 0) {
				printf("\nData Write Failed in PIO Mode.");
				return;
			}
			while (size && (!(irqstat & IRQSTAT_TC))) {
				udelay(100); /* Wait before last byte transfer complete */
				databuf = *((uint *)buffer);
				buffer += 4;
				size -= 4;
				irqstat = esdhc_read32(&regs->irqstat);
				out_le32(&regs->datport, databuf);
			}
			blocks--;
		}
	}
}
#endif

static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
{
	int timeout;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
	uint wml_value;

	wml_value = data->blocksize/4;

	if (data->flags & MMC_DATA_READ) {
		if (wml_value > WML_RD_WML_MAX)
			wml_value = WML_RD_WML_MAX_VAL;

		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
		esdhc_write32(&regs->dsaddr, (u32)data->dest);
	} else {
		if (wml_value > WML_WR_WML_MAX)
			wml_value = WML_WR_WML_MAX_VAL;
		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
			printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
			return TIMEOUT;
		}

		esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
					wml_value << 16);
		esdhc_write32(&regs->dsaddr, (u32)data->src);
	}
#else	/* CONFIG_SYS_FSL_ESDHC_USE_PIO */
	if (!(data->flags & MMC_DATA_READ)) {
		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
			printf("\nThe SD card is locked. "
				"Can not write to a locked card.\n\n");
			return TIMEOUT;
		}
		esdhc_write32(&regs->dsaddr, (u32)data->src);
	} else
		esdhc_write32(&regs->dsaddr, (u32)data->dest);
#endif	/* CONFIG_SYS_FSL_ESDHC_USE_PIO */

	esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);

	/* Calculate the timeout period for data transactions */
	/*
	 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
	 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
	 *  So, Number of SD Clock cycles for 0.25sec should be minimum
	 *		(SD Clock/sec * 0.25 sec) SD Clock cycles
	 *		= (mmc->tran_speed * 1/4) SD Clock cycles
	 * As 1) >=  2)
	 * => (2^(timeout+13)) >= mmc->tran_speed * 1/4
	 * Taking log2 both the sides
	 * => timeout + 13 >= log2(mmc->tran_speed/4)
	 * Rounding up to next power of 2
	 * => timeout + 13 = log2(mmc->tran_speed/4) + 1
	 * => timeout + 13 = fls(mmc->tran_speed/4)
	 */
	timeout = fls(mmc->tran_speed/4);
	timeout -= 13;

	if (timeout > 14)
		timeout = 14;

	if (timeout < 0)
		timeout = 0;

#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
	if ((timeout == 4) || (timeout == 8) || (timeout == 12))
		timeout++;
#endif

	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);

	return 0;
}


/*
 * Sends a command out on the bus.  Takes the mmc pointer,
 * a command pointer, and an optional data pointer.
 */
static int
esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
	uint	xfertyp;
	uint	irqstat;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;

#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		return 0;
#endif

	esdhc_write32(&regs->irqstat, -1);

	sync();

	/* Wait for the bus to be idle */
	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
			(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
		;

	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
		;

	/* Wait at least 8 SD clock cycles before the next command */
	/*
	 * Note: This is way more than 8 cycles, but 1ms seems to
	 * resolve timing issues with some cards
	 */
	udelay(1000);

	/* Set up for a data transfer if we have one */
	if (data) {
		int err;

		err = esdhc_setup_data(mmc, data);
		if(err)
			return err;
	}

	/* Figure out the transfer arguments */
	xfertyp = esdhc_xfertyp(cmd, data);

	/* Send the command */
	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
#if defined(CONFIG_FSL_USDHC)
	esdhc_write32(&regs->mixctrl,
	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
#else
	esdhc_write32(&regs->xfertyp, xfertyp);
#endif
	/* Wait for the command to complete */
	while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
		;

	irqstat = esdhc_read32(&regs->irqstat);
	esdhc_write32(&regs->irqstat, irqstat);

	if (irqstat & CMD_ERR)
		return COMM_ERR;

	if (irqstat & IRQSTAT_CTOE)
		return TIMEOUT;

	/* Copy the response to the response buffer */
	if (cmd->resp_type & MMC_RSP_136) {
		u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;

		cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
		cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
		cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
		cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
		cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
		cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
		cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
		cmd->response[3] = (cmdrsp0 << 8);
	} else
		cmd->response[0] = esdhc_read32(&regs->cmdrsp0);

	/* Wait until all of the blocks are transferred */
	if (data) {
#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
		esdhc_pio_read_write(mmc, data);
#else
		do {
			irqstat = esdhc_read32(&regs->irqstat);

			if (irqstat & IRQSTAT_DTOE)
				return TIMEOUT;

			if (irqstat & DATA_ERR)
				return COMM_ERR;
		} while (!(irqstat & IRQSTAT_TC) &&
				(esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
#endif
	}

	esdhc_write32(&regs->irqstat, -1);

	return 0;
}

void set_sysctl(struct mmc *mmc, uint clock)
{
	int sdhc_clk = gd->sdhc_clk;
	int div, pre_div;
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	uint clk;

	if (clock < mmc->f_min)
		clock = mmc->f_min;

	if (sdhc_clk / 16 > clock) {
		for (pre_div = 2; pre_div < 256; pre_div *= 2)
			if ((sdhc_clk / pre_div) <= (clock * 16))
				break;
	} else
		pre_div = 2;

	for (div = 1; div <= 16; div++)
		if ((sdhc_clk / (div * pre_div)) <= clock)
			break;

	pre_div >>= 1;
	div -= 1;

	clk = (pre_div << 8) | (div << 4);

	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);

	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);

	udelay(10000);

	clk = SYSCTL_PEREN | SYSCTL_CKEN;

	esdhc_setbits32(&regs->sysctl, clk);
}

static void esdhc_set_ios(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;

	/* Set the clock speed */
	set_sysctl(mmc, mmc->clock);

	/* Set the bus width */
	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);

	if (mmc->bus_width == 4)
		esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
	else if (mmc->bus_width == 8)
		esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);

}

static int esdhc_init(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	int timeout = 1000;

	/* Reset the entire host controller */
	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);

	/* Wait until the controller is available */
	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
		udelay(1000);

	/* Enable cache snooping */
	if (cfg && !cfg->no_snoop)
		esdhc_write32(&regs->scr, 0x00000040);

	esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);

	/* Set the initial clock speed */
	mmc_set_clock(mmc, 400000);

	/* Disable the BRR and BWR bits in IRQSTAT */
	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);

	/* Put the PROCTL reg back to the default */
	esdhc_write32(&regs->proctl, PROCTL_INIT);

	/* Set timout to the maximum value */
	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);

	return 0;
}

static int esdhc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
	int timeout = 1000;

	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
		udelay(1000);

	return timeout > 0;
}

static void esdhc_reset(struct fsl_esdhc *regs)
{
	unsigned long timeout = 100; /* wait max 100 ms */

	/* reset the controller */
	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);

	/* hardware clears the bit when it is done */
	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
		udelay(1000);
	if (!timeout)
		printf("MMC/SD: Reset never completed.\n");
}

int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
{
	struct fsl_esdhc *regs;
	struct mmc *mmc;
	u32 caps, voltage_caps;

	if (!cfg)
		return -1;

	mmc = malloc(sizeof(struct mmc));

	sprintf(mmc->name, "FSL_SDHC");
	regs = (struct fsl_esdhc *)cfg->esdhc_base;

	/* First reset the eSDHC controller */
	esdhc_reset(regs);

	mmc->priv = cfg;
	mmc->send_cmd = esdhc_send_cmd;
	mmc->set_ios = esdhc_set_ios;
	mmc->init = esdhc_init;
	mmc->getcd = esdhc_getcd;

	voltage_caps = 0;
	caps = regs->hostcapblt;

#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
			ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
#endif
	if (caps & ESDHC_HOSTCAPBLT_VS18)
		voltage_caps |= MMC_VDD_165_195;
	if (caps & ESDHC_HOSTCAPBLT_VS30)
		voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
	if (caps & ESDHC_HOSTCAPBLT_VS33)
		voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;

#ifdef CONFIG_SYS_SD_VOLTAGE
	mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
#else
	mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
#endif
	if ((mmc->voltages & voltage_caps) == 0) {
		printf("voltage not supported by controller\n");
		return -1;
	}

	mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;

	if (caps & ESDHC_HOSTCAPBLT_HSS)
		mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;

	mmc->f_min = 400000;
	mmc->f_max = MIN(gd->sdhc_clk, 52000000);

	mmc->b_max = 0;
	mmc_register(mmc);

	return 0;
}

int fsl_esdhc_mmc_init(bd_t *bis)
{
	struct fsl_esdhc_cfg *cfg;

	cfg = malloc(sizeof(struct fsl_esdhc_cfg));
	memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
	return fsl_esdhc_initialize(bis, cfg);
}

#ifdef CONFIG_OF_LIBFDT
void fdt_fixup_esdhc(void *blob, bd_t *bd)
{
	const char *compat = "fsl,esdhc";

#ifdef CONFIG_FSL_ESDHC_PIN_MUX
	if (!hwconfig("esdhc")) {
		do_fixup_by_compat(blob, compat, "status", "disabled",
				8 + 1, 1);
		return;
	}
#endif

	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
			       gd->sdhc_clk, 1);

	do_fixup_by_compat(blob, compat, "status", "okay",
			   4 + 1, 1);
}
#endif
Commit	Line	Data
50586ef2	1	/*
d621da00	2	* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
50586ef2 AF	3	* Andy Fleming
	4	*
	5	* Based vaguely on the pxa mmc code:
	6	* (C) Copyright 2003
	7	* Kyle Harris, Nexus Technologies, Inc. [email protected]
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <config.h>
	29	#include <common.h>
	30	#include <command.h>
b33433a6	31	#include <hwconfig.h>
50586ef2 AF	32	#include <mmc.h>
	33	#include <part.h>
	34	#include <malloc.h>
	35	#include <mmc.h>
	36	#include <fsl_esdhc.h>
b33433a6	37	#include <fdt_support.h>
50586ef2 AF	38	#include <asm/io.h>
50586ef2 AF	39
50586ef2 AF	40	DECLARE_GLOBAL_DATA_PTR;
	41
	42	struct fsl_esdhc {
	43	uint dsaddr;
	44	uint blkattr;
	45	uint cmdarg;
	46	uint xfertyp;
	47	uint cmdrsp0;
	48	uint cmdrsp1;
	49	uint cmdrsp2;
	50	uint cmdrsp3;
	51	uint datport;
	52	uint prsstat;
	53	uint proctl;
	54	uint sysctl;
	55	uint irqstat;
	56	uint irqstaten;
	57	uint irqsigen;
	58	uint autoc12err;
	59	uint hostcapblt;
	60	uint wml;
4692708d JL	61	uint mixctrl;
4692708d JL	62	char reserved1[4];
50586ef2 AF	63	uint fevt;
	64	char reserved2[168];
	65	uint hostver;
	66	char reserved3[780];
	67	uint scr;
	68	};
	69
	70	/* Return the XFERTYP flags for a given command and data packet */
	71	uint esdhc_xfertyp(struct mmc_cmd cmd, struct mmc_data data)
	72	{
	73	uint xfertyp = 0;
	74
	75	if (data) {
77c1458d DD	76	xfertyp \|= XFERTYP_DPSEL;
	77	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
	78	xfertyp \|= XFERTYP_DMAEN;
	79	#endif
50586ef2 AF	80	if (data->blocks > 1) {
	81	xfertyp \|= XFERTYP_MSBSEL;
	82	xfertyp \|= XFERTYP_BCEN;
d621da00 JH	83	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
	84	xfertyp \|= XFERTYP_AC12EN;
	85	#endif
50586ef2 AF	86	}
	87
	88	if (data->flags & MMC_DATA_READ)
	89	xfertyp \|= XFERTYP_DTDSEL;
	90	}
	91
	92	if (cmd->resp_type & MMC_RSP_CRC)
	93	xfertyp \|= XFERTYP_CCCEN;
	94	if (cmd->resp_type & MMC_RSP_OPCODE)
	95	xfertyp \|= XFERTYP_CICEN;
	96	if (cmd->resp_type & MMC_RSP_136)
	97	xfertyp \|= XFERTYP_RSPTYP_136;
	98	else if (cmd->resp_type & MMC_RSP_BUSY)
	99	xfertyp \|= XFERTYP_RSPTYP_48_BUSY;
	100	else if (cmd->resp_type & MMC_RSP_PRESENT)
	101	xfertyp \|= XFERTYP_RSPTYP_48;
	102
4571de33 JL	103	#ifdef CONFIG_MX53
	104	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	105	xfertyp \|= XFERTYP_CMDTYP_ABORT;
	106	#endif
50586ef2 AF	107	return XFERTYP_CMD(cmd->cmdidx) \| xfertyp;
	108	}
	109
77c1458d DD	110	#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
	111	/*
	112	* PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
	113	*/
7b43db92	114	static void
77c1458d DD	115	esdhc_pio_read_write(struct mmc mmc, struct mmc_data data)
77c1458d DD	116	{
8eee2bd7 IS	117	struct fsl_esdhc_cfg *cfg = mmc->priv;
8eee2bd7 IS	118	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
77c1458d DD	119	uint blocks;
	120	char *buffer;
	121	uint databuf;
	122	uint size;
	123	uint irqstat;
	124	uint timeout;
	125
	126	if (data->flags & MMC_DATA_READ) {
	127	blocks = data->blocks;
	128	buffer = data->dest;
	129	while (blocks) {
	130	timeout = PIO_TIMEOUT;
	131	size = data->blocksize;
	132	irqstat = esdhc_read32(&regs->irqstat);
	133	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
	134	&& --timeout);
	135	if (timeout <= 0) {
	136	printf("\nData Read Failed in PIO Mode.");
7b43db92	137	return;
77c1458d DD	138	}
	139	while (size && (!(irqstat & IRQSTAT_TC))) {
	140	udelay(100); /* Wait before last byte transfer complete */
	141	irqstat = esdhc_read32(&regs->irqstat);
	142	databuf = in_le32(&regs->datport);
	143	((uint )buffer) = databuf;
	144	buffer += 4;
	145	size -= 4;
	146	}
	147	blocks--;
	148	}
	149	} else {
	150	blocks = data->blocks;
7b43db92	151	buffer = (char *)data->src;
77c1458d DD	152	while (blocks) {
	153	timeout = PIO_TIMEOUT;
	154	size = data->blocksize;
	155	irqstat = esdhc_read32(&regs->irqstat);
	156	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
	157	&& --timeout);
	158	if (timeout <= 0) {
	159	printf("\nData Write Failed in PIO Mode.");
7b43db92	160	return;
77c1458d DD	161	}
	162	while (size && (!(irqstat & IRQSTAT_TC))) {
	163	udelay(100); /* Wait before last byte transfer complete */
	164	databuf = ((uint )buffer);
	165	buffer += 4;
	166	size -= 4;
	167	irqstat = esdhc_read32(&regs->irqstat);
	168	out_le32(&regs->datport, databuf);
	169	}
	170	blocks--;
	171	}
	172	}
	173	}
	174	#endif
	175
50586ef2 AF	176	static int esdhc_setup_data(struct mmc mmc, struct mmc_data data)
50586ef2 AF	177	{
50586ef2	178	int timeout;
c67bee14 SB	179	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	180	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
7b43db92 WD	181	#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
7b43db92 WD	182	uint wml_value;
50586ef2 AF	183
	184	wml_value = data->blocksize/4;
	185
	186	if (data->flags & MMC_DATA_READ) {
32c8cfb2 PJ	187	if (wml_value > WML_RD_WML_MAX)
32c8cfb2 PJ	188	wml_value = WML_RD_WML_MAX_VAL;
50586ef2	189
ab467c51	190	esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
c67bee14	191	esdhc_write32(&regs->dsaddr, (u32)data->dest);
50586ef2	192	} else {
32c8cfb2 PJ	193	if (wml_value > WML_WR_WML_MAX)
32c8cfb2 PJ	194	wml_value = WML_WR_WML_MAX_VAL;
c67bee14	195	if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
50586ef2 AF	196	printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
	197	return TIMEOUT;
	198	}
ab467c51 RZ	199
	200	esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
	201	wml_value << 16);
c67bee14	202	esdhc_write32(&regs->dsaddr, (u32)data->src);
50586ef2	203	}
7b43db92 WD	204	#else /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
	205	if (!(data->flags & MMC_DATA_READ)) {
	206	if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
	207	printf("\nThe SD card is locked. "
	208	"Can not write to a locked card.\n\n");
	209	return TIMEOUT;
	210	}
	211	esdhc_write32(&regs->dsaddr, (u32)data->src);
	212	} else
	213	esdhc_write32(&regs->dsaddr, (u32)data->dest);
	214	#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
50586ef2	215
c67bee14	216	esdhc_write32(&regs->blkattr, data->blocks << 16 \| data->blocksize);
50586ef2 AF	217
50586ef2 AF	218	/* Calculate the timeout period for data transactions */
b71ea336 PJ	219	/*
	220	* 1)Timeout period = (2^(timeout+13)) SD Clock cycles
	221	* 2)Timeout period should be minimum 0.250sec as per SD Card spec
	222	* So, Number of SD Clock cycles for 0.25sec should be minimum
	223	* (SD Clock/sec * 0.25 sec) SD Clock cycles
	224	* = (mmc->tran_speed * 1/4) SD Clock cycles
	225	* As 1) >= 2)
	226	* => (2^(timeout+13)) >= mmc->tran_speed * 1/4
	227	* Taking log2 both the sides
	228	* => timeout + 13 >= log2(mmc->tran_speed/4)
	229	* Rounding up to next power of 2
	230	* => timeout + 13 = log2(mmc->tran_speed/4) + 1
	231	* => timeout + 13 = fls(mmc->tran_speed/4)
	232	*/
	233	timeout = fls(mmc->tran_speed/4);
50586ef2 AF	234	timeout -= 13;
	235
	236	if (timeout > 14)
	237	timeout = 14;
	238
	239	if (timeout < 0)
	240	timeout = 0;
	241
5103a03a KG	242	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
	243	if ((timeout == 4) \|\| (timeout == 8) \|\| (timeout == 12))
	244	timeout++;
	245	#endif
	246
c67bee14	247	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
50586ef2 AF	248
	249	return 0;
	250	}
	251
	252
	253	/*
	254	* Sends a command out on the bus. Takes the mmc pointer,
	255	* a command pointer, and an optional data pointer.
	256	*/
	257	static int
	258	esdhc_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)
	259	{
	260	uint xfertyp;
	261	uint irqstat;
c67bee14 SB	262	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	263	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2	264
d621da00 JH	265	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
	266	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	267	return 0;
	268	#endif
	269
c67bee14	270	esdhc_write32(&regs->irqstat, -1);
50586ef2 AF	271
	272	sync();
	273
	274	/* Wait for the bus to be idle */
c67bee14 SB	275	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) \|\|
	276	(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
	277	;
50586ef2	278
c67bee14 SB	279	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
c67bee14 SB	280	;
50586ef2 AF	281
	282	/* Wait at least 8 SD clock cycles before the next command */
	283	/*
	284	* Note: This is way more than 8 cycles, but 1ms seems to
	285	* resolve timing issues with some cards
	286	*/
	287	udelay(1000);
	288
	289	/* Set up for a data transfer if we have one */
	290	if (data) {
	291	int err;
	292
	293	err = esdhc_setup_data(mmc, data);
	294	if(err)
	295	return err;
	296	}
	297
	298	/* Figure out the transfer arguments */
	299	xfertyp = esdhc_xfertyp(cmd, data);
	300
	301	/* Send the command */
c67bee14	302	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
4692708d JL	303	#if defined(CONFIG_FSL_USDHC)
	304	esdhc_write32(&regs->mixctrl,
	305	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) \| (xfertyp & 0x7F));
	306	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
	307	#else
c67bee14	308	esdhc_write32(&regs->xfertyp, xfertyp);
4692708d	309	#endif
50586ef2	310	/* Wait for the command to complete */
c67bee14 SB	311	while (!(esdhc_read32(&regs->irqstat) & IRQSTAT_CC))
c67bee14 SB	312	;
50586ef2	313
c67bee14 SB	314	irqstat = esdhc_read32(&regs->irqstat);
c67bee14 SB	315	esdhc_write32(&regs->irqstat, irqstat);
50586ef2 AF	316
	317	if (irqstat & CMD_ERR)
	318	return COMM_ERR;
	319
	320	if (irqstat & IRQSTAT_CTOE)
	321	return TIMEOUT;
	322
	323	/* Copy the response to the response buffer */
	324	if (cmd->resp_type & MMC_RSP_136) {
	325	u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
	326
c67bee14 SB	327	cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
	328	cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
	329	cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
	330	cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
998be3dd RV	331	cmd->response[0] = (cmdrsp3 << 8) \| (cmdrsp2 >> 24);
	332	cmd->response[1] = (cmdrsp2 << 8) \| (cmdrsp1 >> 24);
	333	cmd->response[2] = (cmdrsp1 << 8) \| (cmdrsp0 >> 24);
	334	cmd->response[3] = (cmdrsp0 << 8);
50586ef2	335	} else
c67bee14	336	cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
50586ef2 AF	337
	338	/* Wait until all of the blocks are transferred */
	339	if (data) {
77c1458d DD	340	#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
	341	esdhc_pio_read_write(mmc, data);
	342	#else
50586ef2	343	do {
c67bee14	344	irqstat = esdhc_read32(&regs->irqstat);
50586ef2	345
50586ef2 AF	346	if (irqstat & IRQSTAT_DTOE)
50586ef2 AF	347	return TIMEOUT;
63fb5a7e FM	348
	349	if (irqstat & DATA_ERR)
	350	return COMM_ERR;
50586ef2	351	} while (!(irqstat & IRQSTAT_TC) &&
c67bee14	352	(esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
77c1458d	353	#endif
50586ef2 AF	354	}
50586ef2 AF	355
c67bee14	356	esdhc_write32(&regs->irqstat, -1);
50586ef2 AF	357
	358	return 0;
	359	}
	360
	361	void set_sysctl(struct mmc *mmc, uint clock)
	362	{
	363	int sdhc_clk = gd->sdhc_clk;
	364	int div, pre_div;
c67bee14 SB	365	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	366	volatile struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2 AF	367	uint clk;
50586ef2 AF	368
c67bee14 SB	369	if (clock < mmc->f_min)
	370	clock = mmc->f_min;
	371
50586ef2 AF	372	if (sdhc_clk / 16 > clock) {
	373	for (pre_div = 2; pre_div < 256; pre_div *= 2)
	374	if ((sdhc_clk / pre_div) <= (clock * 16))
	375	break;
	376	} else
	377	pre_div = 2;
	378
	379	for (div = 1; div <= 16; div++)
	380	if ((sdhc_clk / (div * pre_div)) <= clock)
	381	break;
	382
	383	pre_div >>= 1;
	384	div -= 1;
	385
	386	clk = (pre_div << 8) \| (div << 4);
	387
cc4d1226	388	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
c67bee14 SB	389
c67bee14 SB	390	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
50586ef2 AF	391
	392	udelay(10000);
	393
cc4d1226	394	clk = SYSCTL_PEREN \| SYSCTL_CKEN;
c67bee14 SB	395
c67bee14 SB	396	esdhc_setbits32(&regs->sysctl, clk);
50586ef2 AF	397	}
	398
	399	static void esdhc_set_ios(struct mmc *mmc)
	400	{
c67bee14 SB	401	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	402	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2 AF	403
	404	/* Set the clock speed */
	405	set_sysctl(mmc, mmc->clock);
	406
	407	/* Set the bus width */
c67bee14	408	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 \| PROCTL_DTW_8);
50586ef2 AF	409
50586ef2 AF	410	if (mmc->bus_width == 4)
c67bee14	411	esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
50586ef2	412	else if (mmc->bus_width == 8)
c67bee14 SB	413	esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
c67bee14 SB	414
50586ef2 AF	415	}
	416
	417	static int esdhc_init(struct mmc *mmc)
	418	{
c67bee14 SB	419	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
c67bee14 SB	420	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
50586ef2 AF	421	int timeout = 1000;
50586ef2 AF	422
c67bee14 SB	423	/* Reset the entire host controller */
	424	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
	425
	426	/* Wait until the controller is available */
	427	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
	428	udelay(1000);
50586ef2	429
2c1764ef S	430	/* Enable cache snooping */
	431	if (cfg && !cfg->no_snoop)
	432	esdhc_write32(&regs->scr, 0x00000040);
	433
c67bee14	434	esdhc_write32(&regs->sysctl, SYSCTL_HCKEN \| SYSCTL_IPGEN);
50586ef2 AF	435
50586ef2 AF	436	/* Set the initial clock speed */
4a6ee172	437	mmc_set_clock(mmc, 400000);
50586ef2 AF	438
50586ef2 AF	439	/* Disable the BRR and BWR bits in IRQSTAT */
c67bee14	440	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR \| IRQSTATEN_BWR);
50586ef2 AF	441
50586ef2 AF	442	/* Put the PROCTL reg back to the default */
c67bee14	443	esdhc_write32(&regs->proctl, PROCTL_INIT);
50586ef2	444
c67bee14 SB	445	/* Set timout to the maximum value */
c67bee14 SB	446	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
50586ef2	447
d48d2e21 TR	448	return 0;
d48d2e21 TR	449	}
50586ef2	450
d48d2e21 TR	451	static int esdhc_getcd(struct mmc *mmc)
	452	{
	453	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	454	struct fsl_esdhc regs = (struct fsl_esdhc )cfg->esdhc_base;
	455	int timeout = 1000;
	456
	457	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
	458	udelay(1000);
c67bee14	459
d48d2e21	460	return timeout > 0;
50586ef2 AF	461	}
50586ef2 AF	462
48bb3bb5 JH	463	static void esdhc_reset(struct fsl_esdhc *regs)
	464	{
	465	unsigned long timeout = 100; /* wait max 100 ms */
	466
	467	/* reset the controller */
	468	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
	469
	470	/* hardware clears the bit when it is done */
	471	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
	472	udelay(1000);
	473	if (!timeout)
	474	printf("MMC/SD: Reset never completed.\n");
	475	}
	476
c67bee14	477	int fsl_esdhc_initialize(bd_t bis, struct fsl_esdhc_cfg cfg)
50586ef2	478	{
c67bee14	479	struct fsl_esdhc *regs;
50586ef2	480	struct mmc *mmc;
030955c2	481	u32 caps, voltage_caps;
50586ef2	482
c67bee14 SB	483	if (!cfg)
	484	return -1;
	485
50586ef2 AF	486	mmc = malloc(sizeof(struct mmc));
50586ef2 AF	487
4692708d	488	sprintf(mmc->name, "FSL_SDHC");
c67bee14 SB	489	regs = (struct fsl_esdhc *)cfg->esdhc_base;
c67bee14 SB	490
48bb3bb5 JH	491	/* First reset the eSDHC controller */
	492	esdhc_reset(regs);
	493
c67bee14	494	mmc->priv = cfg;
50586ef2 AF	495	mmc->send_cmd = esdhc_send_cmd;
	496	mmc->set_ios = esdhc_set_ios;
	497	mmc->init = esdhc_init;
d48d2e21	498	mmc->getcd = esdhc_getcd;
50586ef2	499
030955c2	500	voltage_caps = 0;
50586ef2	501	caps = regs->hostcapblt;
3b4456ec RZ	502
	503	#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
	504	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS \|
	505	ESDHC_HOSTCAPBLT_VS18 \| ESDHC_HOSTCAPBLT_VS30);
	506	#endif
50586ef2	507	if (caps & ESDHC_HOSTCAPBLT_VS18)
030955c2	508	voltage_caps \|= MMC_VDD_165_195;
50586ef2	509	if (caps & ESDHC_HOSTCAPBLT_VS30)
030955c2	510	voltage_caps \|= MMC_VDD_29_30 \| MMC_VDD_30_31;
50586ef2	511	if (caps & ESDHC_HOSTCAPBLT_VS33)
030955c2 LY	512	voltage_caps \|= MMC_VDD_32_33 \| MMC_VDD_33_34;
	513
	514	#ifdef CONFIG_SYS_SD_VOLTAGE
	515	mmc->voltages = CONFIG_SYS_SD_VOLTAGE;
	516	#else
	517	mmc->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34;
	518	#endif
	519	if ((mmc->voltages & voltage_caps) == 0) {
	520	printf("voltage not supported by controller\n");
	521	return -1;
	522	}
50586ef2 AF	523
	524	mmc->host_caps = MMC_MODE_4BIT \| MMC_MODE_8BIT;
	525
	526	if (caps & ESDHC_HOSTCAPBLT_HSS)
	527	mmc->host_caps \|= MMC_MODE_HS_52MHz \| MMC_MODE_HS;
	528
	529	mmc->f_min = 400000;
63786d29	530	mmc->f_max = MIN(gd->sdhc_clk, 52000000);
50586ef2	531
1ed60d7a	532	mmc->b_max = 0;
50586ef2 AF	533	mmc_register(mmc);
	534
	535	return 0;
	536	}
	537
	538	int fsl_esdhc_mmc_init(bd_t *bis)
	539	{
c67bee14 SB	540	struct fsl_esdhc_cfg *cfg;
	541
	542	cfg = malloc(sizeof(struct fsl_esdhc_cfg));
	543	memset(cfg, 0, sizeof(struct fsl_esdhc_cfg));
	544	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
	545	return fsl_esdhc_initialize(bis, cfg);
50586ef2	546	}
b33433a6	547
c67bee14	548	#ifdef CONFIG_OF_LIBFDT
b33433a6 AV	549	void fdt_fixup_esdhc(void blob, bd_t bd)
	550	{
	551	const char *compat = "fsl,esdhc";
b33433a6	552
a6da8b81	553	#ifdef CONFIG_FSL_ESDHC_PIN_MUX
b33433a6	554	if (!hwconfig("esdhc")) {
a6da8b81 CZ	555	do_fixup_by_compat(blob, compat, "status", "disabled",
	556	8 + 1, 1);
	557	return;
b33433a6	558	}
a6da8b81	559	#endif
b33433a6 AV	560
	561	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
	562	gd->sdhc_clk, 1);
a6da8b81 CZ	563
	564	do_fixup_by_compat(blob, compat, "status", "okay",
	565	4 + 1, 1);
b33433a6	566	}
c67bee14	567	#endif