projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 77bc4f9e WD |
1 | /* |
| 2 | * linux/include/asm-arm/hardware/clps7111.h | |
| 3 | * | |
| 4 | * This file contains the hardware definitions of the CLPS7111 internal | |
| 5 | * registers. | |
| 6 | * | |
| 7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License as published by | |
| 11 | * the Free Software Foundation; either version 2 of the License, or | |
| 12 | * (at your option) any later version. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | */ | |
| 23 | #ifndef __ASM_HARDWARE_CLPS7111_H | |
| 24 | #define __ASM_HARDWARE_CLPS7111_H | |
| 25 | ||
| 26 | #define CLPS7111_PHYS_BASE (0x80000000) | |
| 27 | ||
| 28 | #ifndef __ASSEMBLY__ | |
| 29 | #define clps_readb(off) __raw_readb(CLPS7111_BASE + (off)) | |
| 30 | #define clps_readl(off) __raw_readl(CLPS7111_BASE + (off)) | |
| 31 | #define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off)) | |
| 32 | #define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off)) | |
| 33 | #endif | |
| 34 | ||
| 35 | #define PADR (0x0000) | |
| 36 | #define PBDR (0x0001) | |
| 37 | #define PDDR (0x0003) | |
| 38 | #define PADDR (0x0040) | |
| 39 | #define PBDDR (0x0041) | |
| 40 | #define PDDDR (0x0043) | |
| 41 | #define PEDR (0x0080) | |
| 42 | #define PEDDR (0x00c0) | |
| 43 | #define SYSCON1 (0x0100) | |
| 44 | #define SYSFLG1 (0x0140) | |
| 45 | #define MEMCFG1 (0x0180) | |
| 46 | #define MEMCFG2 (0x01c0) | |
| 47 | #define DRFPR (0x0200) | |
| 48 | #define INTSR1 (0x0240) | |
| 49 | #define INTMR1 (0x0280) | |
| 50 | #define LCDCON (0x02c0) | |
| 51 | #define TC1D (0x0300) | |
| 52 | #define TC2D (0x0340) | |
| 53 | #define RTCDR (0x0380) | |
| 54 | #define RTCMR (0x03c0) | |
| 55 | #define PMPCON (0x0400) | |
| 56 | #define CODR (0x0440) | |
| 57 | #define UARTDR1 (0x0480) | |
| 58 | #define UBRLCR1 (0x04c0) | |
| 59 | #define SYNCIO (0x0500) | |
| 60 | #define PALLSW (0x0540) | |
| 61 | #define PALMSW (0x0580) | |
| 62 | #define STFCLR (0x05c0) | |
| 63 | #define BLEOI (0x0600) | |
| 64 | #define MCEOI (0x0640) | |
| 65 | #define TEOI (0x0680) | |
| 66 | #define TC1EOI (0x06c0) | |
| 67 | #define TC2EOI (0x0700) | |
| 68 | #define RTCEOI (0x0740) | |
| 69 | #define UMSEOI (0x0780) | |
| 70 | #define COEOI (0x07c0) | |
| 71 | #define HALT (0x0800) | |
| 72 | #define STDBY (0x0840) | |
| 73 | ||
| 74 | #define FBADDR (0x1000) | |
| 75 | #define SYSCON2 (0x1100) | |
| 76 | #define SYSFLG2 (0x1140) | |
| 77 | #define INTSR2 (0x1240) | |
| 78 | #define INTMR2 (0x1280) | |
| 79 | #define UARTDR2 (0x1480) | |
| 80 | #define UBRLCR2 (0x14c0) | |
| 81 | #define SS2DR (0x1500) | |
| 82 | #define SRXEOF (0x1600) | |
| 83 | #define SS2POP (0x16c0) | |
| 84 | #define KBDEOI (0x1700) | |
| 85 | ||
| 86 | /* common bits: SYSCON1 / SYSCON2 */ | |
| 87 | #define SYSCON_UARTEN (1 << 8) | |
| 88 | ||
| 89 | #define SYSCON1_KBDSCAN(x) ((x) & 15) | |
| 90 | #define SYSCON1_KBDSCANMASK (15) | |
| 91 | #define SYSCON1_TC1M (1 << 4) | |
| 92 | #define SYSCON1_TC1S (1 << 5) | |
| 93 | #define SYSCON1_TC2M (1 << 6) | |
| 94 | #define SYSCON1_TC2S (1 << 7) | |
| 95 | #define SYSCON1_UART1EN SYSCON_UARTEN | |
| 96 | #define SYSCON1_BZTOG (1 << 9) | |
| 97 | #define SYSCON1_BZMOD (1 << 10) | |
| 98 | #define SYSCON1_DBGEN (1 << 11) | |
| 99 | #define SYSCON1_LCDEN (1 << 12) | |
| 100 | #define SYSCON1_CDENTX (1 << 13) | |
| 101 | #define SYSCON1_CDENRX (1 << 14) | |
| 102 | #define SYSCON1_SIREN (1 << 15) | |
| 103 | #define SYSCON1_ADCKSEL(x) (((x) & 3) << 16) | |
| 104 | #define SYSCON1_ADCKSEL_MASK (3 << 16) | |
| 105 | #define SYSCON1_EXCKEN (1 << 18) | |
| 106 | #define SYSCON1_WAKEDIS (1 << 19) | |
| 107 | #define SYSCON1_IRTXM (1 << 20) | |
| 108 | ||
| 109 | /* common bits: SYSFLG1 / SYSFLG2 */ | |
| 110 | #define SYSFLG_UBUSY (1 << 11) | |
| 111 | #define SYSFLG_URXFE (1 << 22) | |
| 112 | #define SYSFLG_UTXFF (1 << 23) | |
| 113 | ||
| 114 | #define SYSFLG1_MCDR (1 << 0) | |
| 115 | #define SYSFLG1_DCDET (1 << 1) | |
| 116 | #define SYSFLG1_WUDR (1 << 2) | |
| 117 | #define SYSFLG1_WUON (1 << 3) | |
| 118 | #define SYSFLG1_CTS (1 << 8) | |
| 119 | #define SYSFLG1_DSR (1 << 9) | |
| 120 | #define SYSFLG1_DCD (1 << 10) | |
| 121 | #define SYSFLG1_UBUSY SYSFLG_UBUSY | |
| 122 | #define SYSFLG1_NBFLG (1 << 12) | |
| 123 | #define SYSFLG1_RSTFLG (1 << 13) | |
| 124 | #define SYSFLG1_PFFLG (1 << 14) | |
| 125 | #define SYSFLG1_CLDFLG (1 << 15) | |
| 126 | #define SYSFLG1_URXFE SYSFLG_URXFE | |
| 127 | #define SYSFLG1_UTXFF SYSFLG_UTXFF | |
| 128 | #define SYSFLG1_CRXFE (1 << 24) | |
| 129 | #define SYSFLG1_CTXFF (1 << 25) | |
| 130 | #define SYSFLG1_SSIBUSY (1 << 26) | |
| 131 | #define SYSFLG1_ID (1 << 29) | |
| 132 | ||
| 133 | #define SYSFLG2_SSRXOF (1 << 0) | |
| 134 | #define SYSFLG2_RESVAL (1 << 1) | |
| 135 | #define SYSFLG2_RESFRM (1 << 2) | |
| 136 | #define SYSFLG2_SS2RXFE (1 << 3) | |
| 137 | #define SYSFLG2_SS2TXFF (1 << 4) | |
| 138 | #define SYSFLG2_SS2TXUF (1 << 5) | |
| 139 | #define SYSFLG2_CKMODE (1 << 6) | |
| 140 | #define SYSFLG2_UBUSY SYSFLG_UBUSY | |
| 141 | #define SYSFLG2_URXFE SYSFLG_URXFE | |
| 142 | #define SYSFLG2_UTXFF SYSFLG_UTXFF | |
| 143 | ||
| 144 | #define LCDCON_GSEN (1 << 30) | |
| 145 | #define LCDCON_GSMD (1 << 31) | |
| 146 | ||
| 147 | #define SYSCON2_SERSEL (1 << 0) | |
| 148 | #define SYSCON2_KBD6 (1 << 1) | |
| 149 | #define SYSCON2_DRAMZ (1 << 2) | |
| 150 | #define SYSCON2_KBWEN (1 << 3) | |
| 151 | #define SYSCON2_SS2TXEN (1 << 4) | |
| 152 | #define SYSCON2_PCCARD1 (1 << 5) | |
| 153 | #define SYSCON2_PCCARD2 (1 << 6) | |
| 154 | #define SYSCON2_SS2RXEN (1 << 7) | |
| 155 | #define SYSCON2_UART2EN SYSCON_UARTEN | |
| 156 | #define SYSCON2_SS2MAEN (1 << 9) | |
| 157 | #define SYSCON2_OSTB (1 << 12) | |
| 158 | #define SYSCON2_CLKENSL (1 << 13) | |
| 159 | #define SYSCON2_BUZFREQ (1 << 14) | |
| 160 | ||
| 161 | /* common bits: UARTDR1 / UARTDR2 */ | |
| 162 | #define UARTDR_FRMERR (1 << 8) | |
| 163 | #define UARTDR_PARERR (1 << 9) | |
| 164 | #define UARTDR_OVERR (1 << 10) | |
| 165 | ||
| 166 | /* common bits: UBRLCR1 / UBRLCR2 */ | |
| 167 | #define UBRLCR_BAUD_MASK ((1 << 12) - 1) | |
| 168 | #define UBRLCR_BREAK (1 << 12) | |
| 169 | #define UBRLCR_PRTEN (1 << 13) | |
| 170 | #define UBRLCR_EVENPRT (1 << 14) | |
| 171 | #define UBRLCR_XSTOP (1 << 15) | |
| 172 | #define UBRLCR_FIFOEN (1 << 16) | |
| 173 | #define UBRLCR_WRDLEN5 (0 << 17) | |
| 174 | #define UBRLCR_WRDLEN6 (1 << 17) | |
| 175 | #define UBRLCR_WRDLEN7 (2 << 17) | |
| 176 | #define UBRLCR_WRDLEN8 (3 << 17) | |
| 177 | #define UBRLCR_WRDLEN_MASK (3 << 17) | |
| 178 | ||
| 179 | #define SYNCIO_SMCKEN (1 << 13) | |
| 180 | #define SYNCIO_TXFRMEN (1 << 14) | |
| 181 | ||
| 182 | #define SYSCON3 0x2200 /* System Control register 3 ----------------------- */ | |
| 183 | #define ADCCON 0x00000001 /* ADC configuration */ | |
| 184 | #define CLKCTL 0x00000006 /* processor clock control */ | |
| 185 | #define CLKCTL_18 0x0 /* 18.432 MHz */ | |
| 186 | #define CLKCTL_36 0x2 /* 36.864 MHz */ | |
| 187 | #define CLKCTL_49 0x4 /* 49.152 MHz */ | |
| 188 | #define CLKCTL_73 0x6 /* 73.728 MHz */ | |
| 189 | #define MCPSEL 0x00000008 /* MCP select */ | |
| 190 | #define ADCCKNSEN 0x000010 /* ADC clock sense */ | |
| 191 | #define VERSN 0x000000e0 /* additional version bits */ | |
| 192 | #define VERSN_SHIFT 5 | |
| 193 | #define FASTWAKE 0x0000100 /* Wakeup clock select: 0=8Hz, 1=4kHz */ | |
| 194 | ||
| 195 | #define INTSR3 0x2240 /* Interrupt Status register 3 --------------------- */ | |
| 196 | #define MCPINT 0x00000001 /* MCP interface interrupt (FIQ) */ | |
| 197 | ||
| 198 | #define INTMR3 0x2280 /* Interrupt Mask register 3 ----------------------- */ | |
| 199 | #define LEDFLSH 0x22C0 /* LED Flash control register ---------------------- */ | |
| 200 | #define LEDFLSH_RATE 0x03 /* flash rate */ | |
| 201 | #define LEDFLSH_RATE_SHIFT 0 | |
| 202 | #define LEDFLSH_DUTY 0x3c /* duty ratio */ | |
| 203 | #define LEDFLSH_DUTY_SHIFT 2 | |
| 204 | #define LEDFLSH_ENABLE 0x40 /* enable */ | |
| 205 | ||
| 206 | #define IO_START CLPS7111_PHYS_BASE | |
| 207 | ||
| 208 | #define IO(offset) (IO_START + (offset)) | |
| 209 | ||
| 210 | #define IO_BYTE(offset) (*(volatile unsigned char *)(IO_START + (offset))) | |
| 211 | #define IO_WORD(offset) (*(volatile unsigned long *)(IO_START + (offset))) | |
| 212 | ||
| 213 | #define IO_PADR IO_BYTE(PADR) | |
| 214 | #define IO_PBDR IO_BYTE(PBDR) | |
| 215 | #define IO_PDDR IO_BYTE(PDDR) | |
| 216 | #define IO_PADDR IO_BYTE(PADDR) | |
| 217 | #define IO_PBDDR IO_BYTE(PBDDR) | |
| 218 | #define IO_PDDDR IO_BYTE(PDDDR) | |
| 219 | #define IO_PEDR IO_BYTE(PEDR) | |
| 220 | #define IO_PEDDR IO_BYTE(PEDDR) | |
| 221 | #define IO_SYSCON IO_WORD(SYSCON) | |
| 222 | #define IO_SYSFLG IO_WORD(SYSFLG) | |
| 223 | #define IO_MEMCFG1 IO_WORD(MEMCFG1) | |
| 224 | #define IO_MEMCFG2 IO_WORD(MEMCFG2) | |
| 225 | #define IO_DRFPR IO_WORD(DRFPR) | |
| 226 | #define IO_INTSR IO_WORD(INTSR) | |
| 227 | #define IO_INTMR IO_WORD(INTMR) | |
| 228 | #define IO_LCDCON IO_WORD(LCDCON) | |
| 229 | #define IO_TC1D IO_WORD(TC1D) | |
| 230 | #define IO_TC2D IO_WORD(TC2D) | |
| 231 | #define IO_RTCDR IO_WORD(RTCDR) | |
| 232 | #define IO_RTCMR IO_WORD(RTCMR) | |
| 233 | #define IO_PMPCON IO_WORD(PMPCON) | |
| 53677ef1 | 234 | #define IO_CODR IO_BYTE(CODR) |
| 77bc4f9e WD |
235 | #define IO_UARTDR IO_WORD(UARTDR) |
| 236 | #define IO_UBRLCR IO_WORD(UBRLCR) | |
| 237 | #define IO_SYNCIO IO_WORD(SYNCIO) | |
| 238 | #define IO_PALLSW IO_WORD(PALLSW) | |
| 239 | #define IO_PALMSW IO_WORD(PALMSW) | |
| 240 | #define IO_STFCLR IO_WORD(STFCLR) | |
| 241 | #define IO_BLEOI IO_WORD(BLEOI) | |
| 242 | #define IO_MCEOI IO_WORD(MCEOI) | |
| 243 | #define IO_TEOI IO_WORD(TEOI) | |
| 244 | #define IO_TC1EOI IO_WORD(TC1EOI) | |
| 245 | #define IO_TC2EOI IO_WORD(TC2EOI) | |
| 246 | #define IO_RTCEOI IO_WORD(RTCEOI) | |
| 247 | #define IO_UMSEOI IO_WORD(UMSEOI) | |
| 248 | #define IO_COEOI IO_WORD(COEOI) | |
| 249 | #define IO_HALT IO_WORD(HALT) | |
| 250 | #define IO_STDBY IO_WORD(STDBY) | |
| 251 | #define IO_SYSCON1 IO_WORD(SYSCON1) | |
| 252 | #define IO_SYSFLG1 IO_WORD(SYSFLG1) | |
| 253 | #define IO_INTSR1 IO_WORD(INTSR1) | |
| 254 | #define IO_INTMR1 IO_WORD(INTMR1) | |
| 255 | #define IO_UARTDR1 IO_WORD(UARTDR1) | |
| 256 | #define IO_UBRLCR1 IO_WORD(UBRLCR1) | |
| 257 | #define IO_FRBADDR IO_WORD(FRBADDR) | |
| 258 | #define IO_SYSCON2 IO_WORD(SYSCON2) | |
| 259 | #define IO_SYSFLG2 IO_WORD(SYSFLG2) | |
| 260 | #define IO_INTSR2 IO_WORD(INTSR2) | |
| 261 | #define IO_INTMR2 IO_WORD(INTMR2) | |
| 262 | #define IO_UARTDR2 IO_WORD(UARTDR2) | |
| 263 | #define IO_UBRLCR2 IO_WORD(UBRLCR2) | |
| 264 | #define IO_KBDEOI IO_WORD(KBDEOI) | |
| 265 | ||
| 266 | #define IO_MCCR IO_WORD(MCCR) | |
| 267 | #define IO_MCDR0 IO_WORD(MCDR0) | |
| 268 | #define IO_MCDR1 IO_WORD(MCDR1) | |
| 269 | #define IO_MCDR2 IO_WORD(MCDR2) | |
| 270 | #define IO_MCSR IO_WORD(MCSR) | |
| 271 | #define IO_SYSCON3 IO_WORD(SYSCON3) | |
| 272 | #define IO_INTSR3 IO_WORD(INTSR3) | |
| 273 | #define IO_INTMR3 IO_WORD(INTMR3) | |
| 274 | #define IO_LEDFLSH IO_WORD(LEDFLSH) | |
| 275 | ||
| 276 | #endif /* __ASM_HARDWARE_CLPS7111_H */ |