]> Git Repo - J-u-boot.git/blame - cmd/mp.c
Merge patch series "Add OPP_LOW support for J7200"
[J-u-boot.git] / cmd / mp.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
ec2b74ff 2/*
0e870980 3 * Copyright 2008-2009 Freescale Semiconductor, Inc.
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4 */
5
ec2b74ff 6#include <command.h>
62f9b654 7#include <cpu_func.h>
03de305e 8#include <vsprintf.h>
ec2b74ff 9
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10static int cpu_status_all(void)
11{
12 unsigned long cpuid;
13
14 for (cpuid = 0; ; cpuid++) {
15 if (!is_core_valid(cpuid)) {
16 if (cpuid == 0) {
17 printf("Core num: %lu is not valid\n", cpuid);
18 return 1;
19 }
20 break;
21 }
22 cpu_status(cpuid);
23 }
24
25 return 0;
26}
27
088f1b19 28static int
09140113 29cpu_cmd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
ec2b74ff 30{
79679d80 31 unsigned long cpuid;
ec2b74ff 32
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33 if (argc == 2 && strncmp(argv[1], "status", 6) == 0)
34 return cpu_status_all();
35
47e26b1b 36 if (argc < 3)
4c12eeb8 37 return CMD_RET_USAGE;
ec2b74ff 38
0b1284eb 39 cpuid = dectoul(argv[1], NULL);
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40 if (!is_core_valid(cpuid)) {
41 printf ("Core num: %lu is not valid\n", cpuid);
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42 return 1;
43 }
44
ec2b74ff 45 if (argc == 3) {
47e26b1b 46 if (strncmp(argv[2], "reset", 5) == 0)
ec2b74ff 47 cpu_reset(cpuid);
47e26b1b 48 else if (strncmp(argv[2], "status", 6) == 0)
ec2b74ff 49 cpu_status(cpuid);
47e26b1b 50 else if (strncmp(argv[2], "disable", 7) == 0)
4194b366 51 return cpu_disable(cpuid);
47e26b1b 52 else
4c12eeb8 53 return CMD_RET_USAGE;
47e26b1b 54
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55 return 0;
56 }
57
58 /* 4 or greater, make sure its release */
47e26b1b 59 if (strncmp(argv[2], "release", 7) != 0)
4c12eeb8 60 return CMD_RET_USAGE;
ec2b74ff 61
47e26b1b 62 if (cpu_release(cpuid, argc - 3, argv + 3))
4c12eeb8 63 return CMD_RET_USAGE;
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64
65 return 0;
66}
67
3616218b 68U_BOOT_LONGHELP(cpu,
088f1b19 69 "<num> reset - Reset cpu <num>\n"
711e5e26 70 "cpu status - Status of all cpus\n"
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71 "cpu <num> status - Status of cpu <num>\n"
72 "cpu <num> disable - Disable cpu <num>\n"
73 "cpu <num> release <addr> [args] - Release cpu <num> at <addr> with [args]"
ec2b74ff 74#ifdef CONFIG_PPC
088f1b19 75 "\n"
79679d80 76 " [args] : <pir> <r3> <r6>\n" \
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77 " pir - processor id (if writeable)\n" \
78 " r3 - value for gpr 3\n" \
ec2b74ff 79 " r6 - value for gpr 6\n" \
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80 "\n" \
81 " Use '-' for any arg if you want the default value.\n" \
79679d80 82 " Default for r3 is <num> and r6 is 0\n" \
ec2b74ff 83 "\n" \
79679d80 84 " When cpu <num> is released r4 and r5 = 0.\n" \
a89c33db 85 " r7 will contain the size of the initial mapped area"
ec2b74ff 86#endif
3616218b 87 );
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88
89U_BOOT_CMD(
6d0f6bcf 90 cpu, CONFIG_SYS_MAXARGS, 1, cpu_cmd,
088f1b19 91 "Multiprocessor CPU boot manipulation and release", cpu_help_text
a89c33db 92);
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