[J-u-boot.git] / board / freescale / p1022ds / ddr.c

/*
 * Copyright 2010 Freescale Semiconductor, Inc.
 * Authors: Srikanth Srinivasan <[email protected]>
 *          Timur Tabi <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>

#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>

struct board_specific_parameters {
	u32 n_ranks;
	u32 datarate_mhz_high;
	u32 clk_adjust;		/* Range: 0-8 */
	u32 cpo;		/* Range: 2-31 */
	u32 write_data_delay;	/* Range: 0-6 */
	u32 force_2t;
};

/*
 * This table contains all valid speeds we want to override with board
 * specific parameters. datarate_mhz_high values need to be in ascending order
 * for each n_ranks group.
 */
static const struct board_specific_parameters dimm0[] = {
	/*
	 * memory controller 0
	 *   num|  hi|  clk| cpo|wrdata|2T
	 * ranks| mhz|adjst|    | delay|
	 */
	{1,  549,    5,  31,     3, 0},
	{1,  850,    5,  31,     5, 0},
	{2,  549,    5,  31,     3, 0},
	{2,  850,    5,  31,     5, 0},
	{}
};

void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
			   unsigned int ctrl_num)
{
	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
	unsigned long ddr_freq;
	unsigned int i;


	if (ctrl_num) {
		printf("Wrong parameter for controller number %d", ctrl_num);
		return;
	}
	if (!pdimm->n_ranks)
		return;

	/* set odt_rd_cfg and odt_wr_cfg. */
	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
		popts->cs_local_opts[i].odt_rd_cfg = 0;
		popts->cs_local_opts[i].odt_wr_cfg = 1;
	}

	pbsp = dimm0;
	/*
	 * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
	 * freqency and n_banks specified in board_specific_parameters table.
	 */
	ddr_freq = get_ddr_freq(0) / 1000000;
	while (pbsp->datarate_mhz_high) {
		if (pbsp->n_ranks == pdimm->n_ranks) {
			if (ddr_freq <= pbsp->datarate_mhz_high) {
				popts->clk_adjust = pbsp->clk_adjust;
				popts->cpo_override = pbsp->cpo;
				popts->write_data_delay =
					pbsp->write_data_delay;
				popts->twot_en = pbsp->force_2t;
				goto found;
			}
			pbsp_highest = pbsp;
		}
		pbsp++;
	}

	if (pbsp_highest) {
		printf("Error: board specific timing not found "
			"for data rate %lu MT/s!\n"
			"Trying to use the highest speed (%u) parameters\n",
			ddr_freq, pbsp_highest->datarate_mhz_high);
		popts->clk_adjust = pbsp->clk_adjust;
		popts->cpo_override = pbsp->cpo;
		popts->write_data_delay = pbsp->write_data_delay;
		popts->twot_en = pbsp->force_2t;
	} else {
		panic("DIMM is not supported by this board");
	}

found:
	popts->half_strength_driver_enable = 1;

	/* Per AN4039, enable ZQ calibration. */
	popts->zq_en = 1;

	/*
	 * For wake-up on ARP, we need auto self refresh enabled
	 */
	popts->auto_self_refresh_en = 1;
	popts->sr_it = 0xb;
}
Commit	Line	Data
c59e1b4d TT	1	/*
	2	* Copyright 2010 Freescale Semiconductor, Inc.
	3	* Authors: Srikanth Srinivasan <[email protected]>
	4	* Timur Tabi <[email protected]>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
c59e1b4d TT	7	*/
	8
	9	#include <common.h>
c59e1b4d	10
5614e71b YS	11	#include <fsl_ddr_sdram.h>
5614e71b YS	12	#include <fsl_ddr_dimm_params.h>
c59e1b4d	13
712cf7ab	14	struct board_specific_parameters {
c59e1b4d	15	u32 n_ranks;
712cf7ab	16	u32 datarate_mhz_high;
c59e1b4d TT	17	u32 clk_adjust; /* Range: 0-8 */
	18	u32 cpo; /* Range: 2-31 */
	19	u32 write_data_delay; /* Range: 0-6 */
0dd38a35	20	u32 force_2t;
712cf7ab	21	};
c59e1b4d	22
c59e1b4d	23	/*
712cf7ab YS	24	* This table contains all valid speeds we want to override with board
	25	* specific parameters. datarate_mhz_high values need to be in ascending order
	26	* for each n_ranks group.
c59e1b4d	27	*/
712cf7ab YS	28	static const struct board_specific_parameters dimm0[] = {
	29	/*
	30	* memory controller 0
	31	* num\| hi\| clk\| cpo\|wrdata\|2T
	32	* ranks\| mhz\|adjst\| \| delay\|
	33	*/
	34	{1, 549, 5, 31, 3, 0},
	35	{1, 850, 5, 31, 5, 0},
	36	{2, 549, 5, 31, 3, 0},
	37	{2, 850, 5, 31, 5, 0},
	38	{}
c59e1b4d TT	39	};
	40
	41	void fsl_ddr_board_options(memctl_options_t popts, dimm_params_t pdimm,
	42	unsigned int ctrl_num)
	43	{
712cf7ab	44	const struct board_specific_parameters pbsp, pbsp_highest = NULL;
c59e1b4d TT	45	unsigned long ddr_freq;
	46	unsigned int i;
	47
712cf7ab YS	48
	49	if (ctrl_num) {
	50	printf("Wrong parameter for controller number %d", ctrl_num);
	51	return;
	52	}
	53	if (!pdimm->n_ranks)
	54	return;
	55
c59e1b4d TT	56	/* set odt_rd_cfg and odt_wr_cfg. */
	57	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
	58	popts->cs_local_opts[i].odt_rd_cfg = 0;
	59	popts->cs_local_opts[i].odt_wr_cfg = 1;
	60	}
	61
712cf7ab	62	pbsp = dimm0;
c59e1b4d TT	63	/*
	64	* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
	65	* freqency and n_banks specified in board_specific_parameters table.
	66	*/
	67	ddr_freq = get_ddr_freq(0) / 1000000;
712cf7ab YS	68	while (pbsp->datarate_mhz_high) {
	69	if (pbsp->n_ranks == pdimm->n_ranks) {
	70	if (ddr_freq <= pbsp->datarate_mhz_high) {
	71	popts->clk_adjust = pbsp->clk_adjust;
	72	popts->cpo_override = pbsp->cpo;
	73	popts->write_data_delay =
	74	pbsp->write_data_delay;
0dd38a35	75	popts->twot_en = pbsp->force_2t;
712cf7ab YS	76	goto found;
	77	}
	78	pbsp_highest = pbsp;
c59e1b4d	79	}
712cf7ab YS	80	pbsp++;
	81	}
	82
	83	if (pbsp_highest) {
	84	printf("Error: board specific timing not found "
	85	"for data rate %lu MT/s!\n"
	86	"Trying to use the highest speed (%u) parameters\n",
	87	ddr_freq, pbsp_highest->datarate_mhz_high);
	88	popts->clk_adjust = pbsp->clk_adjust;
	89	popts->cpo_override = pbsp->cpo;
	90	popts->write_data_delay = pbsp->write_data_delay;
0dd38a35	91	popts->twot_en = pbsp->force_2t;
712cf7ab YS	92	} else {
712cf7ab YS	93	panic("DIMM is not supported by this board");
c59e1b4d TT	94	}
c59e1b4d TT	95
712cf7ab	96	found:
c59e1b4d TT	97	popts->half_strength_driver_enable = 1;
	98
	99	/* Per AN4039, enable ZQ calibration. */
	100	popts->zq_en = 1;
	101
	102	/*
	103	* For wake-up on ARP, we need auto self refresh enabled
	104	*/
	105	popts->auto_self_refresh_en = 1;
	106	popts->sr_it = 0xb;
	107	}