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dm: Add a TPL symbol for simple-bus
[J-u-boot.git] / drivers / mmc / mmc.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 2/*
3 * Copyright 2008, Freescale Semiconductor, Inc
39913ace 4 * Copyright 2020 NXP
272cc70b
AF		 5 * Andy Fleming
6 *
7 * Based vaguely on the Linux code
272cc70b
AF		 8 */
9
10#include <config.h>
11#include <common.h>
e6f6f9e6 12#include <blk.h>
272cc70b 13#include <command.h>
8e3332e2 14#include <dm.h>
f7ae49fc 15#include <log.h>
8e3332e2 16#include <dm/device-internal.h>
d4622df3 17#include <errno.h>
272cc70b
AF		 18#include <mmc.h>
19#include <part.h>
cd93d625 20#include <linux/bitops.h>
c05ed00a 21#include <linux/delay.h>
2051aefe 22#include <power/regulator.h>
272cc70b 23#include <malloc.h>
cf92e05c 24#include <memalign.h>
272cc70b 25#include <linux/list.h>
9b1f942c 26#include <div64.h>
da61fa5f 27#include "mmc_private.h"
272cc70b 28
39320c53
JJH		 29#define DEFAULT_CMD6_TIMEOUT_MS 500
30
aff5d3c8 31static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
b5b838f1 32
e7881d85 33#if !CONFIG_IS_ENABLED(DM_MMC)
c10b85d6 34
6cf8a903 35static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
c10b85d6 36{
d6ad5a0a
LP		 37 if (mmc->cfg->ops->wait_dat0)
38 return mmc->cfg->ops->wait_dat0(mmc, state, timeout_us);
39
c10b85d6
JJH		 40 return -ENOSYS;
41}
42
750121c3 43__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 44{
45 return -1;
46}
47
48int mmc_getwp(struct mmc *mmc)
49{
50 int wp;
51
52 wp = board_mmc_getwp(mmc);
53
d4e1da4e 54 if (wp < 0) {
93bfd616
PA		 55 if (mmc->cfg->ops->getwp)
56 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 57 else
58 wp = 0;
59 }
d23d8d7e
NK		 60
61 return wp;
62}
63
cee9ab7c
JH		 64__weak int board_mmc_getcd(struct mmc *mmc)
65{
11fdade2
SB		 66 return -1;
67}
8ca51e51 68#endif
11fdade2 69
c0c76eba
SG		 70#ifdef CONFIG_MMC_TRACE
71void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
272cc70b 72{
c0c76eba 73 printf("CMD_SEND:%d\n", cmd->cmdidx);
7d5ccb1a 74 printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
c0c76eba 75}
8635ff9e 76
c0c76eba
SG		 77void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
78{
5db2fe3a
RR		 79 int i;
80 u8 *ptr;
81
7863ce58
BM		 82 if (ret) {
83 printf("\t\tRET\t\t\t %d\n", ret);
84 } else {
85 switch (cmd->resp_type) {
86 case MMC_RSP_NONE:
87 printf("\t\tMMC_RSP_NONE\n");
88 break;
89 case MMC_RSP_R1:
7d5ccb1a 90 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
7863ce58
BM		 91 cmd->response[0]);
92 break;
93 case MMC_RSP_R1b:
7d5ccb1a 94 printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
7863ce58
BM		 95 cmd->response[0]);
96 break;
97 case MMC_RSP_R2:
7d5ccb1a 98 printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
7863ce58 99 cmd->response[0]);
7d5ccb1a 100 printf("\t\t \t\t 0x%08x \n",
7863ce58 101 cmd->response[1]);
7d5ccb1a 102 printf("\t\t \t\t 0x%08x \n",
7863ce58 103 cmd->response[2]);
7d5ccb1a 104 printf("\t\t \t\t 0x%08x \n",
7863ce58 105 cmd->response[3]);
5db2fe3a 106 printf("\n");
7863ce58
BM		 107 printf("\t\t\t\t\tDUMPING DATA\n");
108 for (i = 0; i < 4; i++) {
109 int j;
110 printf("\t\t\t\t\t%03d - ", i*4);
111 ptr = (u8 *)&cmd->response[i];
112 ptr += 3;
113 for (j = 0; j < 4; j++)
7d5ccb1a 114 printf("%02x ", *ptr--);
7863ce58
BM		 115 printf("\n");
116 }
117 break;
118 case MMC_RSP_R3:
7d5ccb1a 119 printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
7863ce58
BM		 120 cmd->response[0]);
121 break;
122 default:
123 printf("\t\tERROR MMC rsp not supported\n");
124 break;
53e8e40b 125 }
5db2fe3a 126 }
c0c76eba
SG		 127}
128
129void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
130{
131 int status;
132
133 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
134 printf("CURR STATE:%d\n", status);
135}
5db2fe3a 136#endif
c0c76eba 137
48467e47 138#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG) || CONFIG_VAL(LOGLEVEL) >= LOGL_DEBUG
35f9e196
JJH		 139const char *mmc_mode_name(enum bus_mode mode)
140{
141 static const char *const names[] = {
142 [MMC_LEGACY] = "MMC legacy",
35f9e196
JJH		 143 [MMC_HS] = "MMC High Speed (26MHz)",
144 [SD_HS] = "SD High Speed (50MHz)",
145 [UHS_SDR12] = "UHS SDR12 (25MHz)",
146 [UHS_SDR25] = "UHS SDR25 (50MHz)",
147 [UHS_SDR50] = "UHS SDR50 (100MHz)",
148 [UHS_SDR104] = "UHS SDR104 (208MHz)",
149 [UHS_DDR50] = "UHS DDR50 (50MHz)",
150 [MMC_HS_52] = "MMC High Speed (52MHz)",
151 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
152 [MMC_HS_200] = "HS200 (200MHz)",
3dd2626f 153 [MMC_HS_400] = "HS400 (200MHz)",
44acd492 154 [MMC_HS_400_ES] = "HS400ES (200MHz)",
35f9e196
JJH		 155 };
156
157 if (mode >= MMC_MODES_END)
158 return "Unknown mode";
159 else
160 return names[mode];
161}
162#endif
163
05038576
JJH		 164static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
165{
166 static const int freqs[] = {
1b313aa3 167 [MMC_LEGACY] = 25000000,
05038576
JJH		 168 [MMC_HS] = 26000000,
169 [SD_HS] = 50000000,
1b313aa3
JC		 170 [MMC_HS_52] = 52000000,
171 [MMC_DDR_52] = 52000000,
05038576
JJH		 172 [UHS_SDR12] = 25000000,
173 [UHS_SDR25] = 50000000,
174 [UHS_SDR50] = 100000000,
05038576 175 [UHS_DDR50] = 50000000,
f99c2efe 176 [UHS_SDR104] = 208000000,
05038576 177 [MMC_HS_200] = 200000000,
3dd2626f 178 [MMC_HS_400] = 200000000,
44acd492 179 [MMC_HS_400_ES] = 200000000,
05038576
JJH		 180 };
181
182 if (mode == MMC_LEGACY)
183 return mmc->legacy_speed;
184 else if (mode >= MMC_MODES_END)
185 return 0;
186 else
187 return freqs[mode];
188}
189
35f9e196
JJH		 190static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
191{
192 mmc->selected_mode = mode;
05038576 193 mmc->tran_speed = mmc_mode2freq(mmc, mode);
3862b854 194 mmc->ddr_mode = mmc_is_mode_ddr(mode);
d4d64889
MY		 195 pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
196 mmc->tran_speed / 1000000);
35f9e196
JJH		 197 return 0;
198}
199
e7881d85 200#if !CONFIG_IS_ENABLED(DM_MMC)
c0c76eba
SG		 201int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
202{
203 int ret;
204
205 mmmc_trace_before_send(mmc, cmd);
206 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
207 mmmc_trace_after_send(mmc, cmd, ret);
208
8635ff9e 209 return ret;
272cc70b 210}
8ca51e51 211#endif
272cc70b 212
da129170
SA		 213/**
214 * mmc_send_cmd_retry() - send a command to the mmc device, retrying on error
215 *
216 * @dev: device to receive the command
217 * @cmd: command to send
218 * @data: additional data to send/receive
219 * @retries: how many times to retry; mmc_send_cmd is always called at least
220 * once
185f812c 221 * Return: 0 if ok, -ve on error
da129170
SA		 222 */
223static int mmc_send_cmd_retry(struct mmc *mmc, struct mmc_cmd *cmd,
224 struct mmc_data *data, uint retries)
225{
226 int ret;
227
228 do {
229 ret = mmc_send_cmd(mmc, cmd, data);
230 } while (ret && retries--);
231
232 return ret;
233}
234
235/**
236 * mmc_send_cmd_quirks() - send a command to the mmc device, retrying if a
237 * specific quirk is enabled
238 *
239 * @dev: device to receive the command
240 * @cmd: command to send
241 * @data: additional data to send/receive
242 * @quirk: retry only if this quirk is enabled
243 * @retries: how many times to retry; mmc_send_cmd is always called at least
244 * once
185f812c 245 * Return: 0 if ok, -ve on error
da129170
SA		 246 */
247static int mmc_send_cmd_quirks(struct mmc *mmc, struct mmc_cmd *cmd,
248 struct mmc_data *data, u32 quirk, uint retries)
249{
497b7c6b 250 if (IS_ENABLED(CONFIG_MMC_QUIRKS) && mmc->quirks & quirk)
da129170
SA		 251 return mmc_send_cmd_retry(mmc, cmd, data, retries);
252 else
253 return mmc_send_cmd(mmc, cmd, data);
254}
255
863d1004 256int mmc_send_status(struct mmc *mmc, unsigned int *status)
5d4fc8d9
RR		 257{
258 struct mmc_cmd cmd;
da129170 259 int ret;
5d4fc8d9
RR		 260
261 cmd.cmdidx = MMC_CMD_SEND_STATUS;
262 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 263 if (!mmc_host_is_spi(mmc))
264 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 265
da129170 266 ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 4);
863d1004 267 mmc_trace_state(mmc, &cmd);
da129170
SA		 268 if (!ret)
269 *status = cmd.response[0];
270
271 return ret;
863d1004
JJH		 272}
273
6cf8a903 274int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
863d1004
JJH		 275{
276 unsigned int status;
277 int err;
d0c221fe 278
6cf8a903 279 err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
cd0b80ec
JJH		 280 if (err != -ENOSYS)
281 return err;
282
863d1004
JJH		 283 while (1) {
284 err = mmc_send_status(mmc, &status);
285 if (err)
286 return err;
287
288 if ((status & MMC_STATUS_RDY_FOR_DATA) &&
289 (status & MMC_STATUS_CURR_STATE) !=
290 MMC_STATE_PRG)
291 break;
292
293 if (status & MMC_STATUS_MASK) {
56196826 294#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
863d1004 295 pr_err("Status Error: 0x%08x\n", status);
56196826 296#endif
863d1004
JJH		 297 return -ECOMM;
298 }
5d4fc8d9 299
6cf8a903 300 if (timeout_ms-- <= 0)
1677eef4 301 break;
5d4fc8d9 302
1677eef4
AG		 303 udelay(1000);
304 }
5d4fc8d9 305
6cf8a903 306 if (timeout_ms <= 0) {
56196826 307#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 308 pr_err("Timeout waiting card ready\n");
56196826 309#endif
915ffa52 310 return -ETIMEDOUT;
5d4fc8d9
RR		 311 }
312
313 return 0;
314}
315
da61fa5f 316int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 317{
318 struct mmc_cmd cmd;
319
786e8f81 320 if (mmc->ddr_mode)
d22e3d46
JC		 321 return 0;
322
272cc70b
AF		 323 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
324 cmd.resp_type = MMC_RSP_R1;
325 cmd.cmdarg = len;
272cc70b 326
da129170
SA		 327 return mmc_send_cmd_quirks(mmc, &cmd, NULL,
328 MMC_QUIRK_RETRY_SET_BLOCKLEN, 4);
272cc70b
AF		 329}
330
f99c2efe 331#ifdef MMC_SUPPORTS_TUNING
9815e3ba
JJH		 332static const u8 tuning_blk_pattern_4bit[] = {
333 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
334 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
335 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
336 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
337 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
338 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
339 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
340 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
341};
342
343static const u8 tuning_blk_pattern_8bit[] = {
344 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
345 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
346 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
347 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
348 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
349 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
350 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
351 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
352 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
353 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
354 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
355 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
356 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
357 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
358 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
359 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
360};
361
362int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
363{
364 struct mmc_cmd cmd;
365 struct mmc_data data;
366 const u8 *tuning_block_pattern;
367 int size, err;
368
369 if (mmc->bus_width == 8) {
370 tuning_block_pattern = tuning_blk_pattern_8bit;
371 size = sizeof(tuning_blk_pattern_8bit);
372 } else if (mmc->bus_width == 4) {
373 tuning_block_pattern = tuning_blk_pattern_4bit;
374 size = sizeof(tuning_blk_pattern_4bit);
375 } else {
376 return -EINVAL;
377 }
378
379 ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
380
381 cmd.cmdidx = opcode;
382 cmd.cmdarg = 0;
383 cmd.resp_type = MMC_RSP_R1;
384
385 data.dest = (void *)data_buf;
386 data.blocks = 1;
387 data.blocksize = size;
388 data.flags = MMC_DATA_READ;
389
390 err = mmc_send_cmd(mmc, &cmd, &data);
391 if (err)
392 return err;
393
394 if (memcmp(data_buf, tuning_block_pattern, size))
395 return -EIO;
396
397 return 0;
398}
f99c2efe 399#endif
9815e3ba 400
ff8fef56 401static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 402 lbaint_t blkcnt)
272cc70b
AF		 403{
404 struct mmc_cmd cmd;
405 struct mmc_data data;
406
4a1a06bc
AS		 407 if (blkcnt > 1)
408 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
409 else
410 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 411
412 if (mmc->high_capacity)
4a1a06bc 413 cmd.cmdarg = start;
272cc70b 414 else
4a1a06bc 415 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 416
417 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 418
419 data.dest = dst;
4a1a06bc 420 data.blocks = blkcnt;
272cc70b
AF		 421 data.blocksize = mmc->read_bl_len;
422 data.flags = MMC_DATA_READ;
423
4a1a06bc
AS		 424 if (mmc_send_cmd(mmc, &cmd, &data))
425 return 0;
272cc70b 426
4a1a06bc
AS		 427 if (blkcnt > 1) {
428 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
429 cmd.cmdarg = 0;
430 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 431 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 432#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420 433 pr_err("mmc fail to send stop cmd\n");
56196826 434#endif
4a1a06bc
AS		 435 return 0;
436 }
272cc70b
AF		 437 }
438
4a1a06bc 439 return blkcnt;
272cc70b
AF		 440}
441
145429aa
MV		 442#if !CONFIG_IS_ENABLED(DM_MMC)
443static int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt)
444{
445 if (mmc->cfg->ops->get_b_max)
446 return mmc->cfg->ops->get_b_max(mmc, dst, blkcnt);
447 else
448 return mmc->cfg->b_max;
449}
450#endif
451
c4d660d4 452#if CONFIG_IS_ENABLED(BLK)
7dba0b93 453ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
33fb211d 454#else
7dba0b93
SG		 455ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
456 void *dst)
33fb211d 457#endif
272cc70b 458{
c4d660d4 459#if CONFIG_IS_ENABLED(BLK)
caa4daa2 460 struct blk_desc *block_dev = dev_get_uclass_plat(dev);
33fb211d 461#endif
bcce53d0 462 int dev_num = block_dev->devnum;
873cc1d7 463 int err;
4a1a06bc 464 lbaint_t cur, blocks_todo = blkcnt;
145429aa 465 uint b_max;
4a1a06bc
AS		 466
467 if (blkcnt == 0)
468 return 0;
272cc70b 469
4a1a06bc 470 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 471 if (!mmc)
472 return 0;
473
b5b838f1
MV		 474 if (CONFIG_IS_ENABLED(MMC_TINY))
475 err = mmc_switch_part(mmc, block_dev->hwpart);
476 else
477 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
478
873cc1d7
SW		 479 if (err < 0)
480 return 0;
481
c40fdca6 482 if ((start + blkcnt) > block_dev->lba) {
56196826 483#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d8e3d420
JJH		 484 pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
485 start + blkcnt, block_dev->lba);
56196826 486#endif
d2bf29e3
LW		 487 return 0;
488 }
272cc70b 489
11692991 490 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
d4d64889 491 pr_debug("%s: Failed to set blocklen\n", __func__);
272cc70b 492 return 0;
11692991 493 }
272cc70b 494
145429aa
MV		 495 b_max = mmc_get_b_max(mmc, dst, blkcnt);
496
4a1a06bc 497 do {
145429aa 498 cur = (blocks_todo > b_max) ? b_max : blocks_todo;
11692991 499 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
d4d64889 500 pr_debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 501 return 0;
11692991 502 }
4a1a06bc
AS		 503 blocks_todo -= cur;
504 start += cur;
505 dst += cur * mmc->read_bl_len;
506 } while (blocks_todo > 0);
272cc70b
AF		 507
508 return blkcnt;
509}
510
fdbb873e 511static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 512{
513 struct mmc_cmd cmd;
514 int err;
515
516 udelay(1000);
517
518 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
519 cmd.cmdarg = 0;
520 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 521
522 err = mmc_send_cmd(mmc, &cmd, NULL);
523
524 if (err)
525 return err;
526
527 udelay(2000);
528
529 return 0;
530}
531
f99c2efe 532#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 533static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
534{
535 struct mmc_cmd cmd;
536 int err = 0;
537
538 /*
539 * Send CMD11 only if the request is to switch the card to
540 * 1.8V signalling.
541 */
542 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
543 return mmc_set_signal_voltage(mmc, signal_voltage);
544
545 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
546 cmd.cmdarg = 0;
547 cmd.resp_type = MMC_RSP_R1;
548
549 err = mmc_send_cmd(mmc, &cmd, NULL);
550 if (err)
551 return err;
552
553 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
554 return -EIO;
555
556 /*
557 * The card should drive cmd and dat[0:3] low immediately
558 * after the response of cmd11, but wait 100 us to be sure
559 */
560 err = mmc_wait_dat0(mmc, 0, 100);
561 if (err == -ENOSYS)
562 udelay(100);
563 else if (err)
564 return -ETIMEDOUT;
565
566 /*
567 * During a signal voltage level switch, the clock must be gated
568 * for 5 ms according to the SD spec
569 */
65117182 570 mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
c10b85d6
JJH		 571
572 err = mmc_set_signal_voltage(mmc, signal_voltage);
573 if (err)
574 return err;
575
576 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
577 mdelay(10);
65117182 578 mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
c10b85d6
JJH		 579
580 /*
581 * Failure to switch is indicated by the card holding
582 * dat[0:3] low. Wait for at least 1 ms according to spec
583 */
584 err = mmc_wait_dat0(mmc, 1, 1000);
585 if (err == -ENOSYS)
586 udelay(1000);
587 else if (err)
588 return -ETIMEDOUT;
589
590 return 0;
591}
f99c2efe 592#endif
c10b85d6
JJH		 593
594static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
272cc70b
AF		 595{
596 int timeout = 1000;
597 int err;
598 struct mmc_cmd cmd;
599
1677eef4 600 while (1) {
272cc70b
AF		 601 cmd.cmdidx = MMC_CMD_APP_CMD;
602 cmd.resp_type = MMC_RSP_R1;
603 cmd.cmdarg = 0;
272cc70b
AF		 604
605 err = mmc_send_cmd(mmc, &cmd, NULL);
606
607 if (err)
608 return err;
609
610 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
611 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 612
613 /*
614 * Most cards do not answer if some reserved bits
615 * in the ocr are set. However, Some controller
616 * can set bit 7 (reserved for low voltages), but
617 * how to manage low voltages SD card is not yet
618 * specified.
619 */
d52ebf10 620 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 621 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 622
623 if (mmc->version == SD_VERSION_2)
624 cmd.cmdarg |= OCR_HCS;
625
c10b85d6
JJH		 626 if (uhs_en)
627 cmd.cmdarg |= OCR_S18R;
628
272cc70b
AF		 629 err = mmc_send_cmd(mmc, &cmd, NULL);
630
631 if (err)
632 return err;
633
1677eef4
AG		 634 if (cmd.response[0] & OCR_BUSY)
635 break;
636
637 if (timeout-- <= 0)
915ffa52 638 return -EOPNOTSUPP;
272cc70b 639
1677eef4
AG		 640 udelay(1000);
641 }
272cc70b
AF		 642
643 if (mmc->version != SD_VERSION_2)
644 mmc->version = SD_VERSION_1_0;
645
d52ebf10
TC		 646 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
647 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
648 cmd.resp_type = MMC_RSP_R3;
649 cmd.cmdarg = 0;
d52ebf10
TC		 650
651 err = mmc_send_cmd(mmc, &cmd, NULL);
652
653 if (err)
654 return err;
655 }
656
998be3dd 657 mmc->ocr = cmd.response[0];
272cc70b 658
f99c2efe 659#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 660 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
661 == 0x41000000) {
662 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
663 if (err)
664 return err;
665 }
f99c2efe 666#endif
c10b85d6 667
272cc70b
AF		 668 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
669 mmc->rca = 0;
670
671 return 0;
672}
673
5289b535 674static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 675{
5289b535 676 struct mmc_cmd cmd;
272cc70b
AF		 677 int err;
678
5289b535
AG		 679 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
680 cmd.resp_type = MMC_RSP_R3;
681 cmd.cmdarg = 0;
5a20397b
RH		 682 if (use_arg && !mmc_host_is_spi(mmc))
683 cmd.cmdarg = OCR_HCS |
93bfd616 684 (mmc->cfg->voltages &
a626c8d4
AG		 685 (mmc->ocr & OCR_VOLTAGE_MASK)) |
686 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 687
5289b535 688 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 689 if (err)
690 return err;
5289b535 691 mmc->ocr = cmd.response[0];
e9550449
CLC		 692 return 0;
693}
694
750121c3 695static int mmc_send_op_cond(struct mmc *mmc)
e9550449 696{
e9550449 697 int err, i;
fe95905f
HC		 698 int timeout = 1000;
699 uint start;
e9550449 700
272cc70b
AF		 701 /* Some cards seem to need this */
702 mmc_go_idle(mmc);
703
fe95905f 704 start = get_timer(0);
0cf207ec 705 /* Asking to the card its capabilities */
fe95905f 706 for (i = 0; ; i++) {
5289b535 707 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 708 if (err)
709 return err;
cd6881b5 710
e9550449 711 /* exit if not busy (flag seems to be inverted) */
a626c8d4 712 if (mmc->ocr & OCR_BUSY)
bd47c135 713 break;
fe95905f
HC		 714
715 if (get_timer(start) > timeout)
716 return -ETIMEDOUT;
717 udelay(100);
e9550449 718 }
bd47c135
AG		 719 mmc->op_cond_pending = 1;
720 return 0;
e9550449 721}
cd6881b5 722
750121c3 723static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 724{
725 struct mmc_cmd cmd;
726 int timeout = 1000;
36332b6e 727 ulong start;
e9550449 728 int err;
cd6881b5 729
e9550449 730 mmc->op_cond_pending = 0;
cc17c01f 731 if (!(mmc->ocr & OCR_BUSY)) {
d188b113
YL		 732 /* Some cards seem to need this */
733 mmc_go_idle(mmc);
734
cc17c01f 735 start = get_timer(0);
1677eef4 736 while (1) {
cc17c01f
AG		 737 err = mmc_send_op_cond_iter(mmc, 1);
738 if (err)
739 return err;
1677eef4
AG		 740 if (mmc->ocr & OCR_BUSY)
741 break;
cc17c01f 742 if (get_timer(start) > timeout)
915ffa52 743 return -EOPNOTSUPP;
cc17c01f 744 udelay(100);
1677eef4 745 }
cc17c01f 746 }
272cc70b 747
d52ebf10
TC		 748 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
749 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
750 cmd.resp_type = MMC_RSP_R3;
751 cmd.cmdarg = 0;
d52ebf10
TC		 752
753 err = mmc_send_cmd(mmc, &cmd, NULL);
754
755 if (err)
756 return err;
a626c8d4
AG		 757
758 mmc->ocr = cmd.response[0];
d52ebf10
TC		 759 }
760
272cc70b 761 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 762
763 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 764 mmc->rca = 1;
272cc70b
AF		 765
766 return 0;
767}
768
769
1601ea21 770int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 771{
772 struct mmc_cmd cmd;
773 struct mmc_data data;
774 int err;
775
776 /* Get the Card Status Register */
777 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
778 cmd.resp_type = MMC_RSP_R1;
779 cmd.cmdarg = 0;
272cc70b 780
cdfd1ac6 781 data.dest = (char *)ext_csd;
272cc70b 782 data.blocks = 1;
8bfa195e 783 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 784 data.flags = MMC_DATA_READ;
785
786 err = mmc_send_cmd(mmc, &cmd, &data);
787
788 return err;
789}
790
6892550c
MV		 791static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
792 bool send_status)
272cc70b 793{
bb98b8c5 794 unsigned int status, start;
272cc70b 795 struct mmc_cmd cmd;
6cf8a903 796 int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
513e00b6
JJH		 797 bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
798 (index == EXT_CSD_PART_CONF);
5d4fc8d9 799 int ret;
272cc70b 800
39320c53 801 if (mmc->gen_cmd6_time)
6cf8a903 802 timeout_ms = mmc->gen_cmd6_time * 10;
39320c53 803
513e00b6 804 if (is_part_switch && mmc->part_switch_time)
6cf8a903 805 timeout_ms = mmc->part_switch_time * 10;
513e00b6 806
272cc70b
AF		 807 cmd.cmdidx = MMC_CMD_SWITCH;
808 cmd.resp_type = MMC_RSP_R1b;
809 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 810 (index << 16) |
811 (value << 8);
272cc70b 812
da129170 813 ret = mmc_send_cmd_retry(mmc, &cmd, NULL, 3);
bb98b8c5
JJH		 814 if (ret)
815 return ret;
6892550c 816
bb98b8c5 817 start = get_timer(0);
a9003dc6 818
bb98b8c5 819 /* poll dat0 for rdy/buys status */
6cf8a903 820 ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
bb98b8c5
JJH		 821 if (ret && ret != -ENOSYS)
822 return ret;
5d4fc8d9 823
bb98b8c5 824 /*
44645f87 825 * In cases when neiter allowed to poll by using CMD13 nor we are
bb98b8c5
JJH		 826 * capable of polling by using mmc_wait_dat0, then rely on waiting the
827 * stated timeout to be sufficient.
828 */
44645f87 829 if (ret == -ENOSYS && !send_status) {
6cf8a903 830 mdelay(timeout_ms);
ef5ab0d1
HC		 831 return 0;
832 }
bb98b8c5 833
2349ecff
MV		 834 if (!send_status)
835 return 0;
836
bb98b8c5
JJH		 837 /* Finally wait until the card is ready or indicates a failure
838 * to switch. It doesn't hurt to use CMD13 here even if send_status
6cf8a903 839 * is false, because by now (after 'timeout_ms' ms) the bus should be
bb98b8c5
JJH		 840 * reliable.
841 */
842 do {
843 ret = mmc_send_status(mmc, &status);
844
845 if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
846 pr_debug("switch failed %d/%d/0x%x !\n", set, index,
847 value);
848 return -EIO;
849 }
8e2b0af7
SB		 850 if (!ret && (status & MMC_STATUS_RDY_FOR_DATA) &&
851 (status & MMC_STATUS_CURR_STATE) == MMC_STATE_TRANS)
bb98b8c5
JJH		 852 return 0;
853 udelay(100);
6cf8a903 854 } while (get_timer(start) < timeout_ms);
5d4fc8d9 855
bb98b8c5 856 return -ETIMEDOUT;
272cc70b
AF		 857}
858
6892550c
MV		 859int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
860{
861 return __mmc_switch(mmc, set, index, value, true);
862}
863
0469d846
HS		 864int mmc_boot_wp(struct mmc *mmc)
865{
866 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, 1);
867}
868
19a29ff3
YCLP		 869int mmc_boot_wp_single_partition(struct mmc *mmc, int partition)
870{
871 u8 value;
872 int ret;
873
874 value = EXT_CSD_BOOT_WP_B_PWR_WP_EN;
875
876 if (partition == 0) {
877 value |= EXT_CSD_BOOT_WP_B_SEC_WP_SEL;
878 ret = mmc_switch(mmc,
879 EXT_CSD_CMD_SET_NORMAL,
880 EXT_CSD_BOOT_WP,
881 value);
882 } else if (partition == 1) {
883 value |= EXT_CSD_BOOT_WP_B_SEC_WP_SEL;
884 value |= EXT_CSD_BOOT_WP_B_PWR_WP_SEC_SEL;
885 ret = mmc_switch(mmc,
886 EXT_CSD_CMD_SET_NORMAL,
887 EXT_CSD_BOOT_WP,
888 value);
889 } else {
890 ret = mmc_boot_wp(mmc);
891 }
892
893 return ret;
894}
895
62d77cea 896#if !CONFIG_IS_ENABLED(MMC_TINY)
b9a2a0e2
MV		 897static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
898 bool hsdowngrade)
272cc70b 899{
272cc70b 900 int err;
3862b854
JJH		 901 int speed_bits;
902
903 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
904
905 switch (mode) {
906 case MMC_HS:
907 case MMC_HS_52:
908 case MMC_DDR_52:
909 speed_bits = EXT_CSD_TIMING_HS;
634d4849 910 break;
baef2070 911#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
634d4849
KVA		 912 case MMC_HS_200:
913 speed_bits = EXT_CSD_TIMING_HS200;
914 break;
3dd2626f
PF		 915#endif
916#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
917 case MMC_HS_400:
918 speed_bits = EXT_CSD_TIMING_HS400;
919 break;
44acd492
PF		 920#endif
921#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
922 case MMC_HS_400_ES:
923 speed_bits = EXT_CSD_TIMING_HS400;
924 break;
baef2070 925#endif
3862b854
JJH		 926 case MMC_LEGACY:
927 speed_bits = EXT_CSD_TIMING_LEGACY;
928 break;
929 default:
930 return -EINVAL;
931 }
6892550c
MV		 932
933 err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
934 speed_bits, !hsdowngrade);
3862b854
JJH		 935 if (err)
936 return err;
937
b9a2a0e2
MV		 938#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
939 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
940 /*
941 * In case the eMMC is in HS200/HS400 mode and we are downgrading
942 * to HS mode, the card clock are still running much faster than
943 * the supported HS mode clock, so we can not reliably read out
944 * Extended CSD. Reconfigure the controller to run at HS mode.
945 */
946 if (hsdowngrade) {
947 mmc_select_mode(mmc, MMC_HS);
948 mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
949 }
950#endif
951
3862b854
JJH		 952 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
953 /* Now check to see that it worked */
954 err = mmc_send_ext_csd(mmc, test_csd);
955 if (err)
956 return err;
957
958 /* No high-speed support */
959 if (!test_csd[EXT_CSD_HS_TIMING])
960 return -ENOTSUPP;
961 }
962
963 return 0;
964}
965
966static int mmc_get_capabilities(struct mmc *mmc)
967{
968 u8 *ext_csd = mmc->ext_csd;
969 char cardtype;
272cc70b 970
00e446fa 971 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
272cc70b 972
d52ebf10
TC		 973 if (mmc_host_is_spi(mmc))
974 return 0;
975
272cc70b
AF		 976 /* Only version 4 supports high-speed */
977 if (mmc->version < MMC_VERSION_4)
978 return 0;
979
3862b854 980 if (!ext_csd) {
d8e3d420 981 pr_err("No ext_csd found!\n"); /* this should enver happen */
3862b854
JJH		 982 return -ENOTSUPP;
983 }
272cc70b 984
3862b854 985 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
272cc70b 986
3dd2626f 987 cardtype = ext_csd[EXT_CSD_CARD_TYPE];
bc1e3272 988 mmc->cardtype = cardtype;
272cc70b 989
baef2070 990#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
634d4849
KVA		 991 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
992 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
993 mmc->card_caps |= MMC_MODE_HS200;
994 }
3dd2626f 995#endif
44acd492
PF		 996#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
997 CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
3dd2626f
PF		 998 if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
999 EXT_CSD_CARD_TYPE_HS400_1_8V)) {
1000 mmc->card_caps |= MMC_MODE_HS400;
1001 }
baef2070 1002#endif
d22e3d46 1003 if (cardtype & EXT_CSD_CARD_TYPE_52) {
3862b854 1004 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
d22e3d46 1005 mmc->card_caps |= MMC_MODE_DDR_52MHz;
3862b854 1006 mmc->card_caps |= MMC_MODE_HS_52MHz;
d22e3d46 1007 }
3862b854
JJH		 1008 if (cardtype & EXT_CSD_CARD_TYPE_26)
1009 mmc->card_caps |= MMC_MODE_HS;
272cc70b 1010
44acd492
PF		 1011#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1012 if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
1013 (mmc->card_caps & MMC_MODE_HS400)) {
1014 mmc->card_caps |= MMC_MODE_HS400_ES;
1015 }
1016#endif
1017
272cc70b
AF		 1018 return 0;
1019}
62d77cea 1020#endif
272cc70b 1021
f866a46d
SW		 1022static int mmc_set_capacity(struct mmc *mmc, int part_num)
1023{
1024 switch (part_num) {
1025 case 0:
1026 mmc->capacity = mmc->capacity_user;
1027 break;
1028 case 1:
1029 case 2:
1030 mmc->capacity = mmc->capacity_boot;
1031 break;
1032 case 3:
1033 mmc->capacity = mmc->capacity_rpmb;
1034 break;
1035 case 4:
1036 case 5:
1037 case 6:
1038 case 7:
1039 mmc->capacity = mmc->capacity_gp[part_num - 4];
1040 break;
1041 default:
1042 return -1;
1043 }
1044
c40fdca6 1045 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
f866a46d
SW		 1046
1047 return 0;
1048}
1049
7dba0b93 1050int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
bc897b1d 1051{
f866a46d 1052 int ret;
0538477c 1053 int retry = 3;
bc897b1d 1054
0538477c
JJH		 1055 do {
1056 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1057 EXT_CSD_PART_CONF,
1058 (mmc->part_config & ~PART_ACCESS_MASK)
1059 | (part_num & PART_ACCESS_MASK));
1060 } while (ret && retry--);
f866a46d 1061
6dc93e70
PB		 1062 /*
1063 * Set the capacity if the switch succeeded or was intended
1064 * to return to representing the raw device.
1065 */
873cc1d7 1066 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 1067 ret = mmc_set_capacity(mmc, part_num);
fdbb139f 1068 mmc_get_blk_desc(mmc)->hwpart = part_num;
873cc1d7 1069 }
6dc93e70
PB		 1070
1071 return ret;
bc897b1d
LW		 1072}
1073
cf17789e 1074#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
ac9da0e0
DSC		 1075int mmc_hwpart_config(struct mmc *mmc,
1076 const struct mmc_hwpart_conf *conf,
1077 enum mmc_hwpart_conf_mode mode)
1078{
1079 u8 part_attrs = 0;
1080 u32 enh_size_mult;
1081 u32 enh_start_addr;
1082 u32 gp_size_mult[4];
1083 u32 max_enh_size_mult;
1084 u32 tot_enh_size_mult = 0;
8dda5b0e 1085 u8 wr_rel_set;
ac9da0e0
DSC		 1086 int i, pidx, err;
1087 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1088
1089 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
1090 return -EINVAL;
1091
1092 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
d8e3d420 1093 pr_err("eMMC >= 4.4 required for enhanced user data area\n");
ac9da0e0
DSC		 1094 return -EMEDIUMTYPE;
1095 }
1096
1097 if (!(mmc->part_support & PART_SUPPORT)) {
d8e3d420 1098 pr_err("Card does not support partitioning\n");
ac9da0e0
DSC		 1099 return -EMEDIUMTYPE;
1100 }
1101
1102 if (!mmc->hc_wp_grp_size) {
d8e3d420 1103 pr_err("Card does not define HC WP group size\n");
ac9da0e0
DSC		 1104 return -EMEDIUMTYPE;
1105 }
1106
1107 /* check partition alignment and total enhanced size */
1108 if (conf->user.enh_size) {
1109 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
1110 conf->user.enh_start % mmc->hc_wp_grp_size) {
d8e3d420 1111 pr_err("User data enhanced area not HC WP group "
ac9da0e0
DSC		 1112 "size aligned\n");
1113 return -EINVAL;
1114 }
1115 part_attrs |= EXT_CSD_ENH_USR;
1116 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
1117 if (mmc->high_capacity) {
1118 enh_start_addr = conf->user.enh_start;
1119 } else {
1120 enh_start_addr = (conf->user.enh_start << 9);
1121 }
1122 } else {
1123 enh_size_mult = 0;
1124 enh_start_addr = 0;
1125 }
1126 tot_enh_size_mult += enh_size_mult;
1127
1128 for (pidx = 0; pidx < 4; pidx++) {
1129 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
d8e3d420 1130 pr_err("GP%i partition not HC WP group size "
ac9da0e0
DSC		 1131 "aligned\n", pidx+1);
1132 return -EINVAL;
1133 }
1134 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
1135 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
1136 part_attrs |= EXT_CSD_ENH_GP(pidx);
1137 tot_enh_size_mult += gp_size_mult[pidx];
1138 }
1139 }
1140
1141 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
d8e3d420 1142 pr_err("Card does not support enhanced attribute\n");
ac9da0e0
DSC		 1143 return -EMEDIUMTYPE;
1144 }
1145
1146 err = mmc_send_ext_csd(mmc, ext_csd);
1147 if (err)
1148 return err;
1149
1150 max_enh_size_mult =
1151 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
1152 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
1153 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
1154 if (tot_enh_size_mult > max_enh_size_mult) {
d8e3d420 1155 pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
ac9da0e0
DSC		 1156 tot_enh_size_mult, max_enh_size_mult);
1157 return -EMEDIUMTYPE;
1158 }
1159
8dda5b0e
DSC		 1160 /* The default value of EXT_CSD_WR_REL_SET is device
1161 * dependent, the values can only be changed if the
1162 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
1163 * changed only once and before partitioning is completed. */
1164 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1165 if (conf->user.wr_rel_change) {
1166 if (conf->user.wr_rel_set)
1167 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
1168 else
1169 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
1170 }
1171 for (pidx = 0; pidx < 4; pidx++) {
1172 if (conf->gp_part[pidx].wr_rel_change) {
1173 if (conf->gp_part[pidx].wr_rel_set)
1174 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
1175 else
1176 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
1177 }
1178 }
1179
1180 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
1181 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
1182 puts("Card does not support host controlled partition write "
1183 "reliability settings\n");
1184 return -EMEDIUMTYPE;
1185 }
1186
ac9da0e0
DSC		 1187 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1188 EXT_CSD_PARTITION_SETTING_COMPLETED) {
d8e3d420 1189 pr_err("Card already partitioned\n");
ac9da0e0
DSC		 1190 return -EPERM;
1191 }
1192
1193 if (mode == MMC_HWPART_CONF_CHECK)
1194 return 0;
1195
1196 /* Partitioning requires high-capacity size definitions */
1197 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
1198 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1199 EXT_CSD_ERASE_GROUP_DEF, 1);
1200
1201 if (err)
1202 return err;
1203
1204 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1205
4af66596 1206#if CONFIG_IS_ENABLED(MMC_WRITE)
ac9da0e0
DSC		 1207 /* update erase group size to be high-capacity */
1208 mmc->erase_grp_size =
1209 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
4af66596 1210#endif
ac9da0e0
DSC		 1211
1212 }
1213
1214 /* all OK, write the configuration */
1215 for (i = 0; i < 4; i++) {
1216 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1217 EXT_CSD_ENH_START_ADDR+i,
1218 (enh_start_addr >> (i*8)) & 0xFF);
1219 if (err)
1220 return err;
1221 }
1222 for (i = 0; i < 3; i++) {
1223 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1224 EXT_CSD_ENH_SIZE_MULT+i,
1225 (enh_size_mult >> (i*8)) & 0xFF);
1226 if (err)
1227 return err;
1228 }
1229 for (pidx = 0; pidx < 4; pidx++) {
1230 for (i = 0; i < 3; i++) {
1231 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1232 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
1233 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
1234 if (err)
1235 return err;
1236 }
1237 }
1238 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1239 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
1240 if (err)
1241 return err;
1242
1243 if (mode == MMC_HWPART_CONF_SET)
1244 return 0;
1245
8dda5b0e
DSC		 1246 /* The WR_REL_SET is a write-once register but shall be
1247 * written before setting PART_SETTING_COMPLETED. As it is
1248 * write-once we can only write it when completing the
1249 * partitioning. */
1250 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
1251 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1252 EXT_CSD_WR_REL_SET, wr_rel_set);
1253 if (err)
1254 return err;
1255 }
1256
ac9da0e0
DSC		 1257 /* Setting PART_SETTING_COMPLETED confirms the partition
1258 * configuration but it only becomes effective after power
1259 * cycle, so we do not adjust the partition related settings
1260 * in the mmc struct. */
1261
1262 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1263 EXT_CSD_PARTITION_SETTING,
1264 EXT_CSD_PARTITION_SETTING_COMPLETED);
1265 if (err)
1266 return err;
1267
1268 return 0;
1269}
cf17789e 1270#endif
ac9da0e0 1271
e7881d85 1272#if !CONFIG_IS_ENABLED(DM_MMC)
48972d90
TR		 1273int mmc_getcd(struct mmc *mmc)
1274{
1275 int cd;
1276
1277 cd = board_mmc_getcd(mmc);
1278
d4e1da4e 1279 if (cd < 0) {
93bfd616
PA		 1280 if (mmc->cfg->ops->getcd)
1281 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 1282 else
1283 cd = 1;
1284 }
48972d90
TR		 1285
1286 return cd;
1287}
8ca51e51 1288#endif
48972d90 1289
62d77cea 1290#if !CONFIG_IS_ENABLED(MMC_TINY)
fdbb873e 1291static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 1292{
1293 struct mmc_cmd cmd;
1294 struct mmc_data data;
1295
1296 /* Switch the frequency */
1297 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1298 cmd.resp_type = MMC_RSP_R1;
1299 cmd.cmdarg = (mode << 31) | 0xffffff;
1300 cmd.cmdarg &= ~(0xf << (group * 4));
1301 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 1302
1303 data.dest = (char *)resp;
1304 data.blocksize = 64;
1305 data.blocks = 1;
1306 data.flags = MMC_DATA_READ;
1307
1308 return mmc_send_cmd(mmc, &cmd, &data);
1309}
1310
d0c221fe 1311static int sd_get_capabilities(struct mmc *mmc)
272cc70b
AF		 1312{
1313 int err;
1314 struct mmc_cmd cmd;
18e7c8f6
SM		 1315 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1316 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
272cc70b
AF		 1317 struct mmc_data data;
1318 int timeout;
f99c2efe 1319#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6 1320 u32 sd3_bus_mode;
f99c2efe 1321#endif
272cc70b 1322
e8d5dde4 1323 mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
272cc70b 1324
d52ebf10
TC		 1325 if (mmc_host_is_spi(mmc))
1326 return 0;
1327
272cc70b
AF		 1328 /* Read the SCR to find out if this card supports higher speeds */
1329 cmd.cmdidx = MMC_CMD_APP_CMD;
1330 cmd.resp_type = MMC_RSP_R1;
1331 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1332
1333 err = mmc_send_cmd(mmc, &cmd, NULL);
1334
1335 if (err)
1336 return err;
1337
1338 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1339 cmd.resp_type = MMC_RSP_R1;
1340 cmd.cmdarg = 0;
272cc70b 1341
f781dd38 1342 data.dest = (char *)scr;
272cc70b
AF		 1343 data.blocksize = 8;
1344 data.blocks = 1;
1345 data.flags = MMC_DATA_READ;
1346
da129170 1347 err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
272cc70b 1348
da129170 1349 if (err)
272cc70b 1350 return err;
272cc70b 1351
4e3d89ba
YK		 1352 mmc->scr[0] = __be32_to_cpu(scr[0]);
1353 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 1354
1355 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 1356 case 0:
1357 mmc->version = SD_VERSION_1_0;
1358 break;
1359 case 1:
1360 mmc->version = SD_VERSION_1_10;
1361 break;
1362 case 2:
1363 mmc->version = SD_VERSION_2;
1364 if ((mmc->scr[0] >> 15) & 0x1)
1365 mmc->version = SD_VERSION_3;
1366 break;
1367 default:
1368 mmc->version = SD_VERSION_1_0;
1369 break;
272cc70b
AF		 1370 }
1371
b44c7083
AS		 1372 if (mmc->scr[0] & SD_DATA_4BIT)
1373 mmc->card_caps |= MMC_MODE_4BIT;
1374
272cc70b
AF		 1375 /* Version 1.0 doesn't support switching */
1376 if (mmc->version == SD_VERSION_1_0)
1377 return 0;
1378
1379 timeout = 4;
1380 while (timeout--) {
1381 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 1382 (u8 *)switch_status);
272cc70b
AF		 1383
1384 if (err)
1385 return err;
1386
1387 /* The high-speed function is busy. Try again */
4e3d89ba 1388 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 1389 break;
1390 }
1391
272cc70b 1392 /* If high-speed isn't supported, we return */
d0c221fe
JJH		 1393 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1394 mmc->card_caps |= MMC_CAP(SD_HS);
272cc70b 1395
f99c2efe 1396#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 1397 /* Version before 3.0 don't support UHS modes */
1398 if (mmc->version < SD_VERSION_3)
1399 return 0;
1400
1401 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1402 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1403 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1404 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1405 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1406 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1407 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1408 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1409 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1410 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1411 mmc->card_caps |= MMC_CAP(UHS_DDR50);
f99c2efe 1412#endif
c10b85d6 1413
d0c221fe
JJH		 1414 return 0;
1415}
1416
1417static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1418{
1419 int err;
1420
1421 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
c10b85d6 1422 int speed;
2c3fbf4c 1423
cf345760
MV		 1424 /* SD version 1.00 and 1.01 does not support CMD 6 */
1425 if (mmc->version == SD_VERSION_1_0)
1426 return 0;
1427
c10b85d6 1428 switch (mode) {
e8d5dde4 1429 case MMC_LEGACY:
c10b85d6
JJH		 1430 speed = UHS_SDR12_BUS_SPEED;
1431 break;
1432 case SD_HS:
baef2070
JJH		 1433 speed = HIGH_SPEED_BUS_SPEED;
1434 break;
1435#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1436 case UHS_SDR12:
1437 speed = UHS_SDR12_BUS_SPEED;
1438 break;
c10b85d6
JJH		 1439 case UHS_SDR25:
1440 speed = UHS_SDR25_BUS_SPEED;
1441 break;
1442 case UHS_SDR50:
1443 speed = UHS_SDR50_BUS_SPEED;
1444 break;
1445 case UHS_DDR50:
1446 speed = UHS_DDR50_BUS_SPEED;
1447 break;
1448 case UHS_SDR104:
1449 speed = UHS_SDR104_BUS_SPEED;
1450 break;
baef2070 1451#endif
c10b85d6
JJH		 1452 default:
1453 return -EINVAL;
1454 }
1455
1456 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
d0c221fe
JJH		 1457 if (err)
1458 return err;
1459
a0276f3e 1460 if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
d0c221fe 1461 return -ENOTSUPP;
272cc70b 1462
d0c221fe
JJH		 1463 return 0;
1464}
1465
ec360e64 1466static int sd_select_bus_width(struct mmc *mmc, int w)
d0c221fe
JJH		 1467{
1468 int err;
1469 struct mmc_cmd cmd;
1470
1471 if ((w != 4) && (w != 1))
1472 return -EINVAL;
1473
1474 cmd.cmdidx = MMC_CMD_APP_CMD;
1475 cmd.resp_type = MMC_RSP_R1;
1476 cmd.cmdarg = mmc->rca << 16;
1477
1478 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b
AF		 1479 if (err)
1480 return err;
1481
d0c221fe
JJH		 1482 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1483 cmd.resp_type = MMC_RSP_R1;
1484 if (w == 4)
1485 cmd.cmdarg = 2;
1486 else if (w == 1)
1487 cmd.cmdarg = 0;
1488 err = mmc_send_cmd(mmc, &cmd, NULL);
1489 if (err)
1490 return err;
272cc70b
AF		 1491
1492 return 0;
1493}
62d77cea 1494#endif
272cc70b 1495
5b2e72f3 1496#if CONFIG_IS_ENABLED(MMC_WRITE)
3697e599
PF		 1497static int sd_read_ssr(struct mmc *mmc)
1498{
5b2e72f3
JJH		 1499 static const unsigned int sd_au_size[] = {
1500 0, SZ_16K / 512, SZ_32K / 512,
1501 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
1502 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
1503 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
1504 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
1505 SZ_64M / 512,
1506 };
3697e599
PF		 1507 int err, i;
1508 struct mmc_cmd cmd;
1509 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1510 struct mmc_data data;
3697e599
PF		 1511 unsigned int au, eo, et, es;
1512
1513 cmd.cmdidx = MMC_CMD_APP_CMD;
1514 cmd.resp_type = MMC_RSP_R1;
1515 cmd.cmdarg = mmc->rca << 16;
1516
da129170 1517 err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_APP_CMD, 4);
3697e599
PF		 1518 if (err)
1519 return err;
1520
1521 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1522 cmd.resp_type = MMC_RSP_R1;
1523 cmd.cmdarg = 0;
1524
3697e599
PF		 1525 data.dest = (char *)ssr;
1526 data.blocksize = 64;
1527 data.blocks = 1;
1528 data.flags = MMC_DATA_READ;
1529
da129170
SA		 1530 err = mmc_send_cmd_retry(mmc, &cmd, &data, 3);
1531 if (err)
3697e599 1532 return err;
3697e599
PF		 1533
1534 for (i = 0; i < 16; i++)
1535 ssr[i] = be32_to_cpu(ssr[i]);
1536
1537 au = (ssr[2] >> 12) & 0xF;
1538 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1539 mmc->ssr.au = sd_au_size[au];
1540 es = (ssr[3] >> 24) & 0xFF;
1541 es |= (ssr[2] & 0xFF) << 8;
1542 et = (ssr[3] >> 18) & 0x3F;
1543 if (es && et) {
1544 eo = (ssr[3] >> 16) & 0x3;
1545 mmc->ssr.erase_timeout = (et * 1000) / es;
1546 mmc->ssr.erase_offset = eo * 1000;
1547 }
1548 } else {
d4d64889 1549 pr_debug("Invalid Allocation Unit Size.\n");
3697e599
PF		 1550 }
1551
1552 return 0;
1553}
5b2e72f3 1554#endif
272cc70b
AF		 1555/* frequency bases */
1556/* divided by 10 to be nice to platforms without floating point */
5f837c2c 1557static const int fbase[] = {
272cc70b
AF		 1558 10000,
1559 100000,
1560 1000000,
1561 10000000,
1562};
1563
1564/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1565 * to platforms without floating point.
1566 */
61fe076f 1567static const u8 multipliers[] = {
272cc70b
AF		 1568 0, /* reserved */
1569 10,
1570 12,
1571 13,
1572 15,
1573 20,
1574 25,
1575 30,
1576 35,
1577 40,
1578 45,
1579 50,
1580 55,
1581 60,
1582 70,
1583 80,
1584};
1585
d0c221fe
JJH		 1586static inline int bus_width(uint cap)
1587{
1588 if (cap == MMC_MODE_8BIT)
1589 return 8;
1590 if (cap == MMC_MODE_4BIT)
1591 return 4;
1592 if (cap == MMC_MODE_1BIT)
1593 return 1;
d8e3d420 1594 pr_warn("invalid bus witdh capability 0x%x\n", cap);
d0c221fe
JJH		 1595 return 0;
1596}
1597
e7881d85 1598#if !CONFIG_IS_ENABLED(DM_MMC)
f99c2efe 1599#ifdef MMC_SUPPORTS_TUNING
ec841209
KVA		 1600static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1601{
1602 return -ENOTSUPP;
1603}
f99c2efe 1604#endif
ec841209 1605
2a4d212f 1606static int mmc_set_ios(struct mmc *mmc)
272cc70b 1607{
2a4d212f
KVA		 1608 int ret = 0;
1609
93bfd616 1610 if (mmc->cfg->ops->set_ios)
2a4d212f
KVA		 1611 ret = mmc->cfg->ops->set_ios(mmc);
1612
1613 return ret;
272cc70b 1614}
3602a56a
YG		 1615
1616static int mmc_host_power_cycle(struct mmc *mmc)
1617{
1618 int ret = 0;
1619
1620 if (mmc->cfg->ops->host_power_cycle)
1621 ret = mmc->cfg->ops->host_power_cycle(mmc);
1622
1623 return ret;
1624}
8ca51e51 1625#endif
272cc70b 1626
35f67820 1627int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
272cc70b 1628{
c0fafe64 1629 if (!disable) {
9546eb92
JC		 1630 if (clock > mmc->cfg->f_max)
1631 clock = mmc->cfg->f_max;
272cc70b 1632
9546eb92
JC		 1633 if (clock < mmc->cfg->f_min)
1634 clock = mmc->cfg->f_min;
1635 }
272cc70b
AF		 1636
1637 mmc->clock = clock;
35f67820 1638 mmc->clk_disable = disable;
272cc70b 1639
d2faadb5
JC		 1640 debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
1641
2a4d212f 1642 return mmc_set_ios(mmc);
272cc70b
AF		 1643}
1644
2a4d212f 1645static int mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1646{
1647 mmc->bus_width = width;
1648
2a4d212f 1649 return mmc_set_ios(mmc);
272cc70b
AF		 1650}
1651
4c9d2aaa
JJH		 1652#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1653/*
1654 * helper function to display the capabilities in a human
1655 * friendly manner. The capabilities include bus width and
1656 * supported modes.
1657 */
1658void mmc_dump_capabilities(const char *text, uint caps)
1659{
1660 enum bus_mode mode;
1661
d4d64889 1662 pr_debug("%s: widths [", text);
4c9d2aaa 1663 if (caps & MMC_MODE_8BIT)
d4d64889 1664 pr_debug("8, ");
4c9d2aaa 1665 if (caps & MMC_MODE_4BIT)
d4d64889 1666 pr_debug("4, ");
d0c221fe 1667 if (caps & MMC_MODE_1BIT)
d4d64889
MY		 1668 pr_debug("1, ");
1669 pr_debug("\b\b] modes [");
4c9d2aaa
JJH		 1670 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1671 if (MMC_CAP(mode) & caps)
d4d64889
MY		 1672 pr_debug("%s, ", mmc_mode_name(mode));
1673 pr_debug("\b\b]\n");
4c9d2aaa
JJH		 1674}
1675#endif
1676
d0c221fe
JJH		 1677struct mode_width_tuning {
1678 enum bus_mode mode;
1679 uint widths;
f99c2efe 1680#ifdef MMC_SUPPORTS_TUNING
634d4849 1681 uint tuning;
f99c2efe 1682#endif
d0c221fe
JJH		 1683};
1684
f99c2efe 1685#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
bc1e3272
JJH		 1686int mmc_voltage_to_mv(enum mmc_voltage voltage)
1687{
1688 switch (voltage) {
1689 case MMC_SIGNAL_VOLTAGE_000: return 0;
1690 case MMC_SIGNAL_VOLTAGE_330: return 3300;
1691 case MMC_SIGNAL_VOLTAGE_180: return 1800;
1692 case MMC_SIGNAL_VOLTAGE_120: return 1200;
1693 }
1694 return -EINVAL;
1695}
1696
aff5d3c8
KVA		 1697static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1698{
bc1e3272
JJH		 1699 int err;
1700
1701 if (mmc->signal_voltage == signal_voltage)
1702 return 0;
1703
aff5d3c8 1704 mmc->signal_voltage = signal_voltage;
bc1e3272
JJH		 1705 err = mmc_set_ios(mmc);
1706 if (err)
d4d64889 1707 pr_debug("unable to set voltage (err %d)\n", err);
bc1e3272
JJH		 1708
1709 return err;
aff5d3c8 1710}
f99c2efe
JJH		 1711#else
1712static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1713{
1714 return 0;
1715}
1716#endif
aff5d3c8 1717
62d77cea 1718#if !CONFIG_IS_ENABLED(MMC_TINY)
d0c221fe 1719static const struct mode_width_tuning sd_modes_by_pref[] = {
f99c2efe
JJH		 1720#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
1721#ifdef MMC_SUPPORTS_TUNING
c10b85d6
JJH		 1722 {
1723 .mode = UHS_SDR104,
1724 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1725 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1726 },
f99c2efe 1727#endif
c10b85d6
JJH		 1728 {
1729 .mode = UHS_SDR50,
1730 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1731 },
1732 {
1733 .mode = UHS_DDR50,
1734 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1735 },
1736 {
1737 .mode = UHS_SDR25,
1738 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1739 },
f99c2efe 1740#endif
d0c221fe
JJH		 1741 {
1742 .mode = SD_HS,
1743 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1744 },
f99c2efe 1745#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6
JJH		 1746 {
1747 .mode = UHS_SDR12,
1748 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1749 },
f99c2efe 1750#endif
d0c221fe 1751 {
e8d5dde4 1752 .mode = MMC_LEGACY,
d0c221fe
JJH		 1753 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1754 }
1755};
1756
1757#define for_each_sd_mode_by_pref(caps, mwt) \
1758 for (mwt = sd_modes_by_pref;\
1759 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1760 mwt++) \
1761 if (caps & MMC_CAP(mwt->mode))
1762
01298da3 1763static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
8ac8a263
JJH		 1764{
1765 int err;
d0c221fe
JJH		 1766 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1767 const struct mode_width_tuning *mwt;
f99c2efe 1768#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
c10b85d6 1769 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
f99c2efe
JJH		 1770#else
1771 bool uhs_en = false;
1772#endif
c10b85d6
JJH		 1773 uint caps;
1774
52d241df
JJH		 1775#ifdef DEBUG
1776 mmc_dump_capabilities("sd card", card_caps);
1da8eb59 1777 mmc_dump_capabilities("host", mmc->host_caps);
52d241df 1778#endif
8ac8a263 1779
f49ff799
AP		 1780 if (mmc_host_is_spi(mmc)) {
1781 mmc_set_bus_width(mmc, 1);
e8d5dde4 1782 mmc_select_mode(mmc, MMC_LEGACY);
f49ff799 1783 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
810bc138
PP		 1784#if CONFIG_IS_ENABLED(MMC_WRITE)
1785 err = sd_read_ssr(mmc);
1786 if (err)
1787 pr_warn("unable to read ssr\n");
1788#endif
f49ff799
AP		 1789 return 0;
1790 }
1791
8ac8a263 1792 /* Restrict card's capabilities by what the host can do */
1da8eb59 1793 caps = card_caps & mmc->host_caps;
d0c221fe 1794
c10b85d6
JJH		 1795 if (!uhs_en)
1796 caps &= ~UHS_CAPS;
1797
1798 for_each_sd_mode_by_pref(caps, mwt) {
d0c221fe
JJH		 1799 uint *w;
1800
1801 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
c10b85d6 1802 if (*w & caps & mwt->widths) {
d4d64889
MY		 1803 pr_debug("trying mode %s width %d (at %d MHz)\n",
1804 mmc_mode_name(mwt->mode),
1805 bus_width(*w),
1806 mmc_mode2freq(mmc, mwt->mode) / 1000000);
d0c221fe
JJH		 1807
1808 /* configure the bus width (card + host) */
1809 err = sd_select_bus_width(mmc, bus_width(*w));
1810 if (err)
1811 goto error;
1812 mmc_set_bus_width(mmc, bus_width(*w));
1813
1814 /* configure the bus mode (card) */
1815 err = sd_set_card_speed(mmc, mwt->mode);
1816 if (err)
1817 goto error;
1818
1819 /* configure the bus mode (host) */
1820 mmc_select_mode(mmc, mwt->mode);
65117182
JC		 1821 mmc_set_clock(mmc, mmc->tran_speed,
1822 MMC_CLK_ENABLE);
d0c221fe 1823
f99c2efe 1824#ifdef MMC_SUPPORTS_TUNING
c10b85d6
JJH		 1825 /* execute tuning if needed */
1826 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1827 err = mmc_execute_tuning(mmc,
1828 mwt->tuning);
1829 if (err) {
d4d64889 1830 pr_debug("tuning failed\n");
c10b85d6
JJH		 1831 goto error;
1832 }
1833 }
f99c2efe 1834#endif
c10b85d6 1835
5b2e72f3 1836#if CONFIG_IS_ENABLED(MMC_WRITE)
d0c221fe 1837 err = sd_read_ssr(mmc);
0a4c2b09 1838 if (err)
5b2e72f3
JJH		 1839 pr_warn("unable to read ssr\n");
1840#endif
d0c221fe
JJH		 1841 if (!err)
1842 return 0;
1843
d0c221fe
JJH		 1844error:
1845 /* revert to a safer bus speed */
e8d5dde4 1846 mmc_select_mode(mmc, MMC_LEGACY);
65117182
JC		 1847 mmc_set_clock(mmc, mmc->tran_speed,
1848 MMC_CLK_ENABLE);
d0c221fe
JJH		 1849 }
1850 }
8ac8a263
JJH		 1851 }
1852
d4d64889 1853 pr_err("unable to select a mode\n");
d0c221fe 1854 return -ENOTSUPP;
8ac8a263
JJH		 1855}
1856
7382e691
JJH		 1857/*
1858 * read the compare the part of ext csd that is constant.
1859 * This can be used to check that the transfer is working
1860 * as expected.
1861 */
1862static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
8ac8a263 1863{
7382e691 1864 int err;
dfda9d88 1865 const u8 *ext_csd = mmc->ext_csd;
7382e691
JJH		 1866 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1867
1de06b9f
JJH		 1868 if (mmc->version < MMC_VERSION_4)
1869 return 0;
1870
7382e691
JJH		 1871 err = mmc_send_ext_csd(mmc, test_csd);
1872 if (err)
1873 return err;
1874
1875 /* Only compare read only fields */
1876 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1877 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1878 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1879 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1880 ext_csd[EXT_CSD_REV]
1881 == test_csd[EXT_CSD_REV] &&
1882 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1883 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1884 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1885 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1886 return 0;
1887
1888 return -EBADMSG;
1889}
1890
f99c2efe 1891#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
bc1e3272
JJH		 1892static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1893 uint32_t allowed_mask)
1894{
1895 u32 card_mask = 0;
1896
1897 switch (mode) {
44acd492 1898 case MMC_HS_400_ES:
3dd2626f 1899 case MMC_HS_400:
bc1e3272 1900 case MMC_HS_200:
3dd2626f
PF		 1901 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
1902 EXT_CSD_CARD_TYPE_HS400_1_8V))
bc1e3272 1903 card_mask |= MMC_SIGNAL_VOLTAGE_180;
3dd2626f
PF		 1904 if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
1905 EXT_CSD_CARD_TYPE_HS400_1_2V))
bc1e3272
JJH		 1906 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1907 break;
1908 case MMC_DDR_52:
1909 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
1910 card_mask |= MMC_SIGNAL_VOLTAGE_330 |
1911 MMC_SIGNAL_VOLTAGE_180;
1912 if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
1913 card_mask |= MMC_SIGNAL_VOLTAGE_120;
1914 break;
1915 default:
1916 card_mask |= MMC_SIGNAL_VOLTAGE_330;
1917 break;
1918 }
1919
1920 while (card_mask & allowed_mask) {
1921 enum mmc_voltage best_match;
1922
1923 best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
1924 if (!mmc_set_signal_voltage(mmc, best_match))
1925 return 0;
1926
1927 allowed_mask &= ~best_match;
1928 }
1929
1930 return -ENOTSUPP;
1931}
f99c2efe
JJH		 1932#else
1933static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
1934 uint32_t allowed_mask)
1935{
1936 return 0;
1937}
1938#endif
bc1e3272 1939
3862b854 1940static const struct mode_width_tuning mmc_modes_by_pref[] = {
44acd492
PF		 1941#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1942 {
1943 .mode = MMC_HS_400_ES,
1944 .widths = MMC_MODE_8BIT,
1945 },
1946#endif
3dd2626f
PF		 1947#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1948 {
1949 .mode = MMC_HS_400,
1950 .widths = MMC_MODE_8BIT,
1951 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
1952 },
1953#endif
f99c2efe 1954#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
3862b854
JJH		 1955 {
1956 .mode = MMC_HS_200,
1957 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
634d4849 1958 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
3862b854 1959 },
f99c2efe 1960#endif
3862b854
JJH		 1961 {
1962 .mode = MMC_DDR_52,
1963 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1964 },
1965 {
1966 .mode = MMC_HS_52,
1967 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1968 },
1969 {
1970 .mode = MMC_HS,
1971 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1972 },
1973 {
1974 .mode = MMC_LEGACY,
1975 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1976 }
1977};
1978
1979#define for_each_mmc_mode_by_pref(caps, mwt) \
1980 for (mwt = mmc_modes_by_pref;\
1981 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1982 mwt++) \
1983 if (caps & MMC_CAP(mwt->mode))
1984
1985static const struct ext_csd_bus_width {
1986 uint cap;
1987 bool is_ddr;
1988 uint ext_csd_bits;
1989} ext_csd_bus_width[] = {
1990 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1991 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1992 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1993 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1994 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1995};
1996
3dd2626f
PF		 1997#if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
1998static int mmc_select_hs400(struct mmc *mmc)
1999{
2000 int err;
2001
2002 /* Set timing to HS200 for tuning */
b9a2a0e2 2003 err = mmc_set_card_speed(mmc, MMC_HS_200, false);
3dd2626f
PF		 2004 if (err)
2005 return err;
2006
2007 /* configure the bus mode (host) */
2008 mmc_select_mode(mmc, MMC_HS_200);
2009 mmc_set_clock(mmc, mmc->tran_speed, false);
2010
2011 /* execute tuning if needed */
8c968808 2012 mmc->hs400_tuning = 1;
3dd2626f 2013 err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
8c968808 2014 mmc->hs400_tuning = 0;
3dd2626f
PF		 2015 if (err) {
2016 debug("tuning failed\n");
2017 return err;
2018 }
2019
2020 /* Set back to HS */
5cf12031 2021 mmc_set_card_speed(mmc, MMC_HS, true);
3dd2626f 2022
d271e105
YL		 2023 err = mmc_hs400_prepare_ddr(mmc);
2024 if (err)
2025 return err;
2026
3dd2626f
PF		 2027 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
2028 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
2029 if (err)
2030 return err;
2031
b9a2a0e2 2032 err = mmc_set_card_speed(mmc, MMC_HS_400, false);
3dd2626f
PF		 2033 if (err)
2034 return err;
2035
2036 mmc_select_mode(mmc, MMC_HS_400);
2037 err = mmc_set_clock(mmc, mmc->tran_speed, false);
2038 if (err)
2039 return err;
2040
2041 return 0;
2042}
2043#else
2044static int mmc_select_hs400(struct mmc *mmc)
2045{
2046 return -ENOTSUPP;
2047}
2048#endif
2049
44acd492
PF		 2050#if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
2051#if !CONFIG_IS_ENABLED(DM_MMC)
2052static int mmc_set_enhanced_strobe(struct mmc *mmc)
2053{
2054 return -ENOTSUPP;
2055}
2056#endif
2057static int mmc_select_hs400es(struct mmc *mmc)
2058{
2059 int err;
2060
2061 err = mmc_set_card_speed(mmc, MMC_HS, true);
2062 if (err)
2063 return err;
2064
2065 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
2066 EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
2067 EXT_CSD_BUS_WIDTH_STROBE);
2068 if (err) {
2069 printf("switch to bus width for hs400 failed\n");
2070 return err;
2071 }
2072 /* TODO: driver strength */
2073 err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
2074 if (err)
2075 return err;
2076
2077 mmc_select_mode(mmc, MMC_HS_400_ES);
2078 err = mmc_set_clock(mmc, mmc->tran_speed, false);
2079 if (err)
2080 return err;
2081
2082 return mmc_set_enhanced_strobe(mmc);
2083}
2084#else
2085static int mmc_select_hs400es(struct mmc *mmc)
2086{
2087 return -ENOTSUPP;
2088}
2089#endif
2090
3862b854
JJH		 2091#define for_each_supported_width(caps, ddr, ecbv) \
2092 for (ecbv = ext_csd_bus_width;\
2093 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
2094 ecbv++) \
2095 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
2096
01298da3 2097static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
7382e691 2098{
52ff04a2 2099 int err = 0;
3862b854
JJH		 2100 const struct mode_width_tuning *mwt;
2101 const struct ext_csd_bus_width *ecbw;
8ac8a263 2102
52d241df
JJH		 2103#ifdef DEBUG
2104 mmc_dump_capabilities("mmc", card_caps);
1da8eb59 2105 mmc_dump_capabilities("host", mmc->host_caps);
52d241df
JJH		 2106#endif
2107
f49ff799
AP		 2108 if (mmc_host_is_spi(mmc)) {
2109 mmc_set_bus_width(mmc, 1);
2110 mmc_select_mode(mmc, MMC_LEGACY);
2111 mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
2112 return 0;
2113 }
2114
8ac8a263 2115 /* Restrict card's capabilities by what the host can do */
1da8eb59 2116 card_caps &= mmc->host_caps;
8ac8a263
JJH		 2117
2118 /* Only version 4 of MMC supports wider bus widths */
2119 if (mmc->version < MMC_VERSION_4)
2120 return 0;
2121
dfda9d88 2122 if (!mmc->ext_csd) {
d4d64889 2123 pr_debug("No ext_csd found!\n"); /* this should enver happen */
dfda9d88
JJH		 2124 return -ENOTSUPP;
2125 }
2126
b9a2a0e2 2127#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
fb8c2e8f
YL		 2128 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
2129 CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
b9a2a0e2
MV		 2130 /*
2131 * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
2132 * before doing anything else, since a transition from either of
2133 * the HS200/HS400 mode directly to legacy mode is not supported.
2134 */
2135 if (mmc->selected_mode == MMC_HS_200 ||
fb8c2e8f
YL		 2136 mmc->selected_mode == MMC_HS_400 ||
2137 mmc->selected_mode == MMC_HS_400_ES)
b9a2a0e2
MV		 2138 mmc_set_card_speed(mmc, MMC_HS, true);
2139 else
2140#endif
2141 mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
01298da3
JJH		 2142
2143 for_each_mmc_mode_by_pref(card_caps, mwt) {
2144 for_each_supported_width(card_caps & mwt->widths,
3862b854 2145 mmc_is_mode_ddr(mwt->mode), ecbw) {
bc1e3272 2146 enum mmc_voltage old_voltage;
d4d64889
MY		 2147 pr_debug("trying mode %s width %d (at %d MHz)\n",
2148 mmc_mode_name(mwt->mode),
2149 bus_width(ecbw->cap),
2150 mmc_mode2freq(mmc, mwt->mode) / 1000000);
bc1e3272
JJH		 2151 old_voltage = mmc->signal_voltage;
2152 err = mmc_set_lowest_voltage(mmc, mwt->mode,
2153 MMC_ALL_SIGNAL_VOLTAGE);
2154 if (err)
2155 continue;
2156
3862b854
JJH		 2157 /* configure the bus width (card + host) */
2158 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2159 EXT_CSD_BUS_WIDTH,
2160 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
2161 if (err)
2162 goto error;
2163 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
8ac8a263 2164
3dd2626f
PF		 2165 if (mwt->mode == MMC_HS_400) {
2166 err = mmc_select_hs400(mmc);
2167 if (err) {
2168 printf("Select HS400 failed %d\n", err);
2169 goto error;
2170 }
44acd492
PF		 2171 } else if (mwt->mode == MMC_HS_400_ES) {
2172 err = mmc_select_hs400es(mmc);
2173 if (err) {
2174 printf("Select HS400ES failed %d\n",
2175 err);
2176 goto error;
2177 }
3dd2626f
PF		 2178 } else {
2179 /* configure the bus speed (card) */
b9a2a0e2 2180 err = mmc_set_card_speed(mmc, mwt->mode, false);
3862b854
JJH		 2181 if (err)
2182 goto error;
8ac8a263 2183
3dd2626f
PF		 2184 /*
2185 * configure the bus width AND the ddr mode
2186 * (card). The host side will be taken care
2187 * of in the next step
2188 */
2189 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
2190 err = mmc_switch(mmc,
2191 EXT_CSD_CMD_SET_NORMAL,
2192 EXT_CSD_BUS_WIDTH,
2193 ecbw->ext_csd_bits);
2194 if (err)
2195 goto error;
2196 }
2197
2198 /* configure the bus mode (host) */
2199 mmc_select_mode(mmc, mwt->mode);
2200 mmc_set_clock(mmc, mmc->tran_speed,
2201 MMC_CLK_ENABLE);
f99c2efe 2202#ifdef MMC_SUPPORTS_TUNING
8ac8a263 2203
3dd2626f
PF		 2204 /* execute tuning if needed */
2205 if (mwt->tuning) {
2206 err = mmc_execute_tuning(mmc,
2207 mwt->tuning);
2208 if (err) {
58896458 2209 pr_debug("tuning failed : %d\n", err);
3dd2626f
PF		 2210 goto error;
2211 }
634d4849 2212 }
f99c2efe 2213#endif
3dd2626f 2214 }
634d4849 2215
3862b854
JJH		 2216 /* do a transfer to check the configuration */
2217 err = mmc_read_and_compare_ext_csd(mmc);
2218 if (!err)
2219 return 0;
2220error:
bc1e3272 2221 mmc_set_signal_voltage(mmc, old_voltage);
64dbd86b 2222 /* if an error occurred, revert to a safer bus mode */
3862b854
JJH		 2223 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2224 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
2225 mmc_select_mode(mmc, MMC_LEGACY);
2226 mmc_set_bus_width(mmc, 1);
2227 }
8ac8a263
JJH		 2228 }
2229
58896458 2230 pr_err("unable to select a mode : %d\n", err);
8ac8a263 2231
3862b854 2232 return -ENOTSUPP;
8ac8a263 2233}
62d77cea
MV		 2234#endif
2235
2236#if CONFIG_IS_ENABLED(MMC_TINY)
2237DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
2238#endif
8ac8a263 2239
dfda9d88 2240static int mmc_startup_v4(struct mmc *mmc)
c744b6f6
JJH		 2241{
2242 int err, i;
2243 u64 capacity;
2244 bool has_parts = false;
2245 bool part_completed;
58a6fb7b
JJH		 2246 static const u32 mmc_versions[] = {
2247 MMC_VERSION_4,
2248 MMC_VERSION_4_1,
2249 MMC_VERSION_4_2,
2250 MMC_VERSION_4_3,
ace1bed3 2251 MMC_VERSION_4_4,
58a6fb7b
JJH		 2252 MMC_VERSION_4_41,
2253 MMC_VERSION_4_5,
2254 MMC_VERSION_5_0,
2255 MMC_VERSION_5_1
2256 };
2257
62d77cea
MV		 2258#if CONFIG_IS_ENABLED(MMC_TINY)
2259 u8 *ext_csd = ext_csd_bkup;
2260
2261 if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
2262 return 0;
2263
2264 if (!mmc->ext_csd)
2265 memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
2266
2267 err = mmc_send_ext_csd(mmc, ext_csd);
2268 if (err)
2269 goto error;
2270
2271 /* store the ext csd for future reference */
2272 if (!mmc->ext_csd)
2273 mmc->ext_csd = ext_csd;
2274#else
f7d5dffc 2275 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
c744b6f6
JJH		 2276
2277 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
2278 return 0;
2279
2280 /* check ext_csd version and capacity */
2281 err = mmc_send_ext_csd(mmc, ext_csd);
2282 if (err)
f7d5dffc
JJH		 2283 goto error;
2284
2285 /* store the ext csd for future reference */
2286 if (!mmc->ext_csd)
2287 mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
2288 if (!mmc->ext_csd)
2289 return -ENOMEM;
2290 memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
62d77cea 2291#endif
76584e33 2292 if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
58a6fb7b
JJH		 2293 return -EINVAL;
2294
2295 mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
2296
2297 if (mmc->version >= MMC_VERSION_4_2) {
c744b6f6
JJH		 2298 /*
2299 * According to the JEDEC Standard, the value of
2300 * ext_csd's capacity is valid if the value is more
2301 * than 2GB
2302 */
2303 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
2304 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
2305 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
2306 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
2307 capacity *= MMC_MAX_BLOCK_LEN;
2308 if ((capacity >> 20) > 2 * 1024)
2309 mmc->capacity_user = capacity;
2310 }
2311
39320c53
JJH		 2312 if (mmc->version >= MMC_VERSION_4_5)
2313 mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
2314
c744b6f6
JJH		 2315 /* The partition data may be non-zero but it is only
2316 * effective if PARTITION_SETTING_COMPLETED is set in
2317 * EXT_CSD, so ignore any data if this bit is not set,
2318 * except for enabling the high-capacity group size
2319 * definition (see below).
2320 */
2321 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
2322 EXT_CSD_PARTITION_SETTING_COMPLETED);
2323
513e00b6
JJH		 2324 mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
2325 /* Some eMMC set the value too low so set a minimum */
2326 if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
2327 mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
2328
c744b6f6
JJH		 2329 /* store the partition info of emmc */
2330 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
2331 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
2332 ext_csd[EXT_CSD_BOOT_MULT])
2333 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
2334 if (part_completed &&
2335 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
2336 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
2337
2338 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
2339
2340 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
2341
2342 for (i = 0; i < 4; i++) {
2343 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
2344 uint mult = (ext_csd[idx + 2] << 16) +
2345 (ext_csd[idx + 1] << 8) + ext_csd[idx];
2346 if (mult)
2347 has_parts = true;
2348 if (!part_completed)
2349 continue;
2350 mmc->capacity_gp[i] = mult;
2351 mmc->capacity_gp[i] *=
2352 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2353 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2354 mmc->capacity_gp[i] <<= 19;
2355 }
2356
173c06df 2357#ifndef CONFIG_SPL_BUILD
c744b6f6
JJH		 2358 if (part_completed) {
2359 mmc->enh_user_size =
2360 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
2361 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
2362 ext_csd[EXT_CSD_ENH_SIZE_MULT];
2363 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
2364 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
2365 mmc->enh_user_size <<= 19;
2366 mmc->enh_user_start =
2367 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
2368 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
2369 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
2370 ext_csd[EXT_CSD_ENH_START_ADDR];
2371 if (mmc->high_capacity)
2372 mmc->enh_user_start <<= 9;
2373 }
173c06df 2374#endif
c744b6f6
JJH		 2375
2376 /*
2377 * Host needs to enable ERASE_GRP_DEF bit if device is
2378 * partitioned. This bit will be lost every time after a reset
2379 * or power off. This will affect erase size.
2380 */
2381 if (part_completed)
2382 has_parts = true;
2383 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
2384 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
2385 has_parts = true;
2386 if (has_parts) {
2387 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
2388 EXT_CSD_ERASE_GROUP_DEF, 1);
2389
2390 if (err)
f7d5dffc 2391 goto error;
c744b6f6
JJH		 2392
2393 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
2394 }
2395
2396 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
e6fa5a54 2397#if CONFIG_IS_ENABLED(MMC_WRITE)
c744b6f6
JJH		 2398 /* Read out group size from ext_csd */
2399 mmc->erase_grp_size =
2400 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
e6fa5a54 2401#endif
c744b6f6
JJH		 2402 /*
2403 * if high capacity and partition setting completed
2404 * SEC_COUNT is valid even if it is smaller than 2 GiB
2405 * JEDEC Standard JESD84-B45, 6.2.4
2406 */
2407 if (mmc->high_capacity && part_completed) {
2408 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
2409 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
2410 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
2411 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
2412 capacity *= MMC_MAX_BLOCK_LEN;
2413 mmc->capacity_user = capacity;
2414 }
e6fa5a54
JJH		 2415 }
2416#if CONFIG_IS_ENABLED(MMC_WRITE)
2417 else {
c744b6f6
JJH		 2418 /* Calculate the group size from the csd value. */
2419 int erase_gsz, erase_gmul;
2420
2421 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
2422 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
2423 mmc->erase_grp_size = (erase_gsz + 1)
2424 * (erase_gmul + 1);
2425 }
e6fa5a54 2426#endif
b7a6e2c9 2427#if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
c744b6f6
JJH		 2428 mmc->hc_wp_grp_size = 1024
2429 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
2430 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
b7a6e2c9 2431#endif
c744b6f6
JJH		 2432
2433 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
2434
2435 return 0;
f7d5dffc
JJH		 2436error:
2437 if (mmc->ext_csd) {
62d77cea 2438#if !CONFIG_IS_ENABLED(MMC_TINY)
f7d5dffc 2439 free(mmc->ext_csd);
62d77cea 2440#endif
f7d5dffc
JJH		 2441 mmc->ext_csd = NULL;
2442 }
2443 return err;
c744b6f6
JJH		 2444}
2445
fdbb873e 2446static int mmc_startup(struct mmc *mmc)
272cc70b 2447{
f866a46d 2448 int err, i;
272cc70b 2449 uint mult, freq;
c744b6f6 2450 u64 cmult, csize;
272cc70b 2451 struct mmc_cmd cmd;
c40fdca6 2452 struct blk_desc *bdesc;
272cc70b 2453
d52ebf10
TC		 2454#ifdef CONFIG_MMC_SPI_CRC_ON
2455 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
2456 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
2457 cmd.resp_type = MMC_RSP_R1;
2458 cmd.cmdarg = 1;
d52ebf10 2459 err = mmc_send_cmd(mmc, &cmd, NULL);
d52ebf10
TC		 2460 if (err)
2461 return err;
2462 }
2463#endif
2464
272cc70b 2465 /* Put the Card in Identify Mode */
d52ebf10
TC		 2466 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
2467 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 2468 cmd.resp_type = MMC_RSP_R2;
2469 cmd.cmdarg = 0;
272cc70b 2470
da129170 2471 err = mmc_send_cmd_quirks(mmc, &cmd, NULL, MMC_QUIRK_RETRY_SEND_CID, 4);
272cc70b
AF		 2472 if (err)
2473 return err;
2474
2475 memcpy(mmc->cid, cmd.response, 16);
2476
2477 /*
2478 * For MMC cards, set the Relative Address.
2479 * For SD cards, get the Relatvie Address.
2480 * This also puts the cards into Standby State
2481 */
d52ebf10
TC		 2482 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2483 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
2484 cmd.cmdarg = mmc->rca << 16;
2485 cmd.resp_type = MMC_RSP_R6;
272cc70b 2486
d52ebf10 2487 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2488
d52ebf10
TC		 2489 if (err)
2490 return err;
272cc70b 2491
d52ebf10
TC		 2492 if (IS_SD(mmc))
2493 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
2494 }
272cc70b
AF		 2495
2496 /* Get the Card-Specific Data */
2497 cmd.cmdidx = MMC_CMD_SEND_CSD;
2498 cmd.resp_type = MMC_RSP_R2;
2499 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 2500
2501 err = mmc_send_cmd(mmc, &cmd, NULL);
2502
2503 if (err)
2504 return err;
2505
998be3dd
RV		 2506 mmc->csd[0] = cmd.response[0];
2507 mmc->csd[1] = cmd.response[1];
2508 mmc->csd[2] = cmd.response[2];
2509 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 2510
2511 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 2512 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 2513
2514 switch (version) {
53e8e40b
BM		 2515 case 0:
2516 mmc->version = MMC_VERSION_1_2;
2517 break;
2518 case 1:
2519 mmc->version = MMC_VERSION_1_4;
2520 break;
2521 case 2:
2522 mmc->version = MMC_VERSION_2_2;
2523 break;
2524 case 3:
2525 mmc->version = MMC_VERSION_3;
2526 break;
2527 case 4:
2528 mmc->version = MMC_VERSION_4;
2529 break;
2530 default:
2531 mmc->version = MMC_VERSION_1_2;
2532 break;
272cc70b
AF		 2533 }
2534 }
2535
2536 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 2537 freq = fbase[(cmd.response[0] & 0x7)];
2538 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b 2539
35f9e196 2540 mmc->legacy_speed = freq * mult;
35f9e196 2541 mmc_select_mode(mmc, MMC_LEGACY);
272cc70b 2542
ab71188c 2543 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 2544 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
e6fa5a54 2545#if CONFIG_IS_ENABLED(MMC_WRITE)
272cc70b
AF		 2546
2547 if (IS_SD(mmc))
2548 mmc->write_bl_len = mmc->read_bl_len;
2549 else
998be3dd 2550 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
e6fa5a54 2551#endif
272cc70b
AF		 2552
2553 if (mmc->high_capacity) {
2554 csize = (mmc->csd[1] & 0x3f) << 16
2555 | (mmc->csd[2] & 0xffff0000) >> 16;
2556 cmult = 8;
2557 } else {
2558 csize = (mmc->csd[1] & 0x3ff) << 2
2559 | (mmc->csd[2] & 0xc0000000) >> 30;
2560 cmult = (mmc->csd[2] & 0x00038000) >> 15;
2561 }
2562
f866a46d
SW		 2563 mmc->capacity_user = (csize + 1) << (cmult + 2);
2564 mmc->capacity_user *= mmc->read_bl_len;
2565 mmc->capacity_boot = 0;
2566 mmc->capacity_rpmb = 0;
2567 for (i = 0; i < 4; i++)
2568 mmc->capacity_gp[i] = 0;
272cc70b 2569
8bfa195e
SG		 2570 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
2571 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 2572
e6fa5a54 2573#if CONFIG_IS_ENABLED(MMC_WRITE)
8bfa195e
SG		 2574 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
2575 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2576#endif
272cc70b 2577
ab71188c
MN		 2578 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
2579 cmd.cmdidx = MMC_CMD_SET_DSR;
2580 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
2581 cmd.resp_type = MMC_RSP_NONE;
2582 if (mmc_send_cmd(mmc, &cmd, NULL))
d8e3d420 2583 pr_warn("MMC: SET_DSR failed\n");
ab71188c
MN		 2584 }
2585
272cc70b 2586 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 2587 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
2588 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 2589 cmd.resp_type = MMC_RSP_R1;
d52ebf10 2590 cmd.cmdarg = mmc->rca << 16;
d52ebf10 2591 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 2592
d52ebf10
TC		 2593 if (err)
2594 return err;
2595 }
272cc70b 2596
e6f99a56
LW		 2597 /*
2598 * For SD, its erase group is always one sector
2599 */
e6fa5a54 2600#if CONFIG_IS_ENABLED(MMC_WRITE)
e6f99a56 2601 mmc->erase_grp_size = 1;
e6fa5a54 2602#endif
bc897b1d 2603 mmc->part_config = MMCPART_NOAVAILABLE;
1937e5aa 2604
dfda9d88 2605 err = mmc_startup_v4(mmc);
c744b6f6
JJH		 2606 if (err)
2607 return err;
d23e2c09 2608
c40fdca6 2609 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
f866a46d
SW		 2610 if (err)
2611 return err;
2612
62d77cea
MV		 2613#if CONFIG_IS_ENABLED(MMC_TINY)
2614 mmc_set_clock(mmc, mmc->legacy_speed, false);
e8d5dde4 2615 mmc_select_mode(mmc, MMC_LEGACY);
62d77cea
MV		 2616 mmc_set_bus_width(mmc, 1);
2617#else
01298da3
JJH		 2618 if (IS_SD(mmc)) {
2619 err = sd_get_capabilities(mmc);
2620 if (err)
2621 return err;
2622 err = sd_select_mode_and_width(mmc, mmc->card_caps);
2623 } else {
2624 err = mmc_get_capabilities(mmc);
2625 if (err)
2626 return err;
8adf50ef 2627 err = mmc_select_mode_and_width(mmc, mmc->card_caps);
01298da3 2628 }
62d77cea 2629#endif
272cc70b
AF		 2630 if (err)
2631 return err;
2632
01298da3 2633 mmc->best_mode = mmc->selected_mode;
ad5fd922 2634
5af8f45c
AG		 2635 /* Fix the block length for DDR mode */
2636 if (mmc->ddr_mode) {
2637 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2638#if CONFIG_IS_ENABLED(MMC_WRITE)
5af8f45c 2639 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
e6fa5a54 2640#endif
5af8f45c
AG		 2641 }
2642
272cc70b 2643 /* fill in device description */
c40fdca6
SG		 2644 bdesc = mmc_get_blk_desc(mmc);
2645 bdesc->lun = 0;
2646 bdesc->hwpart = 0;
2647 bdesc->type = 0;
2648 bdesc->blksz = mmc->read_bl_len;
2649 bdesc->log2blksz = LOG2(bdesc->blksz);
2650 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
fc011f64
SS		 2651#if !defined(CONFIG_SPL_BUILD) || \
2652 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
27084c03 2653 !CONFIG_IS_ENABLED(USE_TINY_PRINTF))
c40fdca6 2654 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
babce5f6
TH		 2655 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2656 (mmc->cid[3] >> 16) & 0xffff);
c40fdca6 2657 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
babce5f6
TH		 2658 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2659 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2660 (mmc->cid[2] >> 24) & 0xff);
c40fdca6 2661 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
babce5f6 2662 (mmc->cid[2] >> 16) & 0xf);
56196826 2663#else
c40fdca6
SG		 2664 bdesc->vendor[0] = 0;
2665 bdesc->product[0] = 0;
2666 bdesc->revision[0] = 0;
56196826 2667#endif
272cc70b 2668
eef05fd3
AP		 2669#if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
2670 part_init(bdesc);
2671#endif
2672
272cc70b
AF		 2673 return 0;
2674}
2675
fdbb873e 2676static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 2677{
2678 struct mmc_cmd cmd;
2679 int err;
2680
2681 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2682 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 2683 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 2684 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 2685
2686 err = mmc_send_cmd(mmc, &cmd, NULL);
2687
2688 if (err)
2689 return err;
2690
998be3dd 2691 if ((cmd.response[0] & 0xff) != 0xaa)
915ffa52 2692 return -EOPNOTSUPP;
272cc70b
AF		 2693 else
2694 mmc->version = SD_VERSION_2;
2695
2696 return 0;
2697}
2698
c4d660d4 2699#if !CONFIG_IS_ENABLED(DM_MMC)
95de9ab2
PK		 2700/* board-specific MMC power initializations. */
2701__weak void board_mmc_power_init(void)
2702{
2703}
05cbeb7c 2704#endif
95de9ab2 2705
2051aefe
PF		 2706static int mmc_power_init(struct mmc *mmc)
2707{
c4d660d4 2708#if CONFIG_IS_ENABLED(DM_MMC)
06ec045f 2709#if CONFIG_IS_ENABLED(DM_REGULATOR)
2051aefe
PF		 2710 int ret;
2711
2712 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
06ec045f
JJH		 2713 &mmc->vmmc_supply);
2714 if (ret)
d4d64889 2715 pr_debug("%s: No vmmc supply\n", mmc->dev->name);
2051aefe 2716
06ec045f
JJH		 2717 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2718 &mmc->vqmmc_supply);
2719 if (ret)
d4d64889 2720 pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
fb7c3beb
KVA		 2721#endif
2722#else /* !CONFIG_DM_MMC */
2723 /*
2724 * Driver model should use a regulator, as above, rather than calling
2725 * out to board code.
2726 */
2727 board_mmc_power_init();
2728#endif
2729 return 0;
2730}
2731
2732/*
2733 * put the host in the initial state:
2734 * - turn on Vdd (card power supply)
2735 * - configure the bus width and clock to minimal values
2736 */
2737static void mmc_set_initial_state(struct mmc *mmc)
2738{
2739 int err;
2740
2741 /* First try to set 3.3V. If it fails set to 1.8V */
2742 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2743 if (err != 0)
2744 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2745 if (err != 0)
d8e3d420 2746 pr_warn("mmc: failed to set signal voltage\n");
fb7c3beb
KVA		 2747
2748 mmc_select_mode(mmc, MMC_LEGACY);
2749 mmc_set_bus_width(mmc, 1);
65117182 2750 mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
fb7c3beb 2751}
06ec045f 2752
fb7c3beb
KVA		 2753static int mmc_power_on(struct mmc *mmc)
2754{
2755#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
06ec045f 2756 if (mmc->vmmc_supply) {
fb7c3beb
KVA		 2757 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2758
b3dc016c 2759 if (ret && ret != -EACCES) {
58896458 2760 printf("Error enabling VMMC supply : %d\n", ret);
06ec045f
JJH		 2761 return ret;
2762 }
2051aefe 2763 }
05cbeb7c 2764#endif
fb7c3beb
KVA		 2765 return 0;
2766}
2767
2768static int mmc_power_off(struct mmc *mmc)
2769{
65117182 2770 mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
fb7c3beb
KVA		 2771#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2772 if (mmc->vmmc_supply) {
2773 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2774
b3dc016c 2775 if (ret && ret != -EACCES) {
58896458 2776 pr_debug("Error disabling VMMC supply : %d\n", ret);
fb7c3beb
KVA		 2777 return ret;
2778 }
2779 }
2051aefe
PF		 2780#endif
2781 return 0;
2782}
2783
fb7c3beb
KVA		 2784static int mmc_power_cycle(struct mmc *mmc)
2785{
2786 int ret;
2787
2788 ret = mmc_power_off(mmc);
2789 if (ret)
2790 return ret;
3602a56a
YG		 2791
2792 ret = mmc_host_power_cycle(mmc);
2793 if (ret)
2794 return ret;
2795
fb7c3beb
KVA		 2796 /*
2797 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2798 * to be on the safer side.
2799 */
2800 udelay(2000);
2801 return mmc_power_on(mmc);
2802}
2803
a4c577f9 2804int mmc_get_op_cond(struct mmc *mmc, bool quiet)
272cc70b 2805{
c10b85d6 2806 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
afd5932b 2807 int err;
272cc70b 2808
bc897b1d
LW		 2809 if (mmc->has_init)
2810 return 0;
2811
2051aefe
PF		 2812 err = mmc_power_init(mmc);
2813 if (err)
2814 return err;
95de9ab2 2815
83dc4227
KVA		 2816#ifdef CONFIG_MMC_QUIRKS
2817 mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
d4a5fa31
JJ		 2818 MMC_QUIRK_RETRY_SEND_CID |
2819 MMC_QUIRK_RETRY_APP_CMD;
83dc4227
KVA		 2820#endif
2821
04a2ea24
JJH		 2822 err = mmc_power_cycle(mmc);
2823 if (err) {
2824 /*
2825 * if power cycling is not supported, we should not try
2826 * to use the UHS modes, because we wouldn't be able to
2827 * recover from an error during the UHS initialization.
2828 */
d4d64889 2829 pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
04a2ea24
JJH		 2830 uhs_en = false;
2831 mmc->host_caps &= ~UHS_CAPS;
2832 err = mmc_power_on(mmc);
2833 }
fb7c3beb
KVA		 2834 if (err)
2835 return err;
2836
e7881d85 2837#if CONFIG_IS_ENABLED(DM_MMC)
390f9bdd
YL		 2838 /*
2839 * Re-initialization is needed to clear old configuration for
2840 * mmc rescan.
2841 */
2842 err = mmc_reinit(mmc);
8ca51e51 2843#else
ab769f22 2844 /* made sure it's not NULL earlier */
93bfd616 2845 err = mmc->cfg->ops->init(mmc);
390f9bdd 2846#endif
272cc70b
AF		 2847 if (err)
2848 return err;
786e8f81 2849 mmc->ddr_mode = 0;
aff5d3c8 2850
c10b85d6 2851retry:
fb7c3beb 2852 mmc_set_initial_state(mmc);
318a7a57 2853
272cc70b
AF		 2854 /* Reset the Card */
2855 err = mmc_go_idle(mmc);
2856
2857 if (err)
2858 return err;
2859
f5624b10 2860 /* The internal partition reset to user partition(0) at every CMD0 */
c40fdca6 2861 mmc_get_blk_desc(mmc)->hwpart = 0;
bc897b1d 2862
272cc70b 2863 /* Test for SD version 2 */
afd5932b 2864 err = mmc_send_if_cond(mmc);
272cc70b 2865
272cc70b 2866 /* Now try to get the SD card's operating condition */
c10b85d6
JJH		 2867 err = sd_send_op_cond(mmc, uhs_en);
2868 if (err && uhs_en) {
2869 uhs_en = false;
2870 mmc_power_cycle(mmc);
2871 goto retry;
2872 }
272cc70b
AF		 2873
2874 /* If the command timed out, we check for an MMC card */
915ffa52 2875 if (err == -ETIMEDOUT) {
272cc70b
AF		 2876 err = mmc_send_op_cond(mmc);
2877
bd47c135 2878 if (err) {
56196826 2879#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
a4c577f9
T		 2880 if (!quiet)
2881 pr_err("Card did not respond to voltage select! : %d\n", err);
56196826 2882#endif
915ffa52 2883 return -EOPNOTSUPP;
272cc70b
AF		 2884 }
2885 }
2886
6c09eba5
JN		 2887 return err;
2888}
2889
2890int mmc_start_init(struct mmc *mmc)
2891{
2892 bool no_card;
2893 int err = 0;
2894
2895 /*
2896 * all hosts are capable of 1 bit bus-width and able to use the legacy
2897 * timings.
2898 */
e8d5dde4 2899 mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(MMC_LEGACY) |
19f7a34a
AG		 2900 MMC_MODE_1BIT;
2901
2902 if (IS_ENABLED(CONFIG_MMC_SPEED_MODE_SET)) {
2903 if (mmc->user_speed_mode != MMC_MODES_END) {
2904 int i;
2905 /* set host caps */
2906 if (mmc->host_caps & MMC_CAP(mmc->user_speed_mode)) {
2907 /* Remove all existing speed capabilities */
2908 for (i = MMC_LEGACY; i < MMC_MODES_END; i++)
2909 mmc->host_caps &= ~MMC_CAP(i);
2910 mmc->host_caps |= (MMC_CAP(mmc->user_speed_mode)
2911 | MMC_CAP(MMC_LEGACY) |
2912 MMC_MODE_1BIT);
2913 } else {
2914 pr_err("bus_mode requested is not supported\n");
2915 return -EINVAL;
2916 }
2917 }
2918 }
32860bdb
FA		 2919#if CONFIG_IS_ENABLED(DM_MMC)
2920 mmc_deferred_probe(mmc);
2921#endif
6c09eba5 2922#if !defined(CONFIG_MMC_BROKEN_CD)
6c09eba5
JN		 2923 no_card = mmc_getcd(mmc) == 0;
2924#else
2925 no_card = 0;
2926#endif
2927#if !CONFIG_IS_ENABLED(DM_MMC)
fea3939d 2928 /* we pretend there's no card when init is NULL */
6c09eba5
JN		 2929 no_card = no_card || (mmc->cfg->ops->init == NULL);
2930#endif
2931 if (no_card) {
2932 mmc->has_init = 0;
2933#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
2934 pr_err("MMC: no card present\n");
2935#endif
2936 return -ENOMEDIUM;
2937 }
2938
a4c577f9 2939 err = mmc_get_op_cond(mmc, false);
6c09eba5 2940
bd47c135 2941 if (!err)
e9550449
CLC		 2942 mmc->init_in_progress = 1;
2943
2944 return err;
2945}
2946
2947static int mmc_complete_init(struct mmc *mmc)
2948{
2949 int err = 0;
2950
bd47c135 2951 mmc->init_in_progress = 0;
e9550449
CLC		 2952 if (mmc->op_cond_pending)
2953 err = mmc_complete_op_cond(mmc);
2954
2955 if (!err)
2956 err = mmc_startup(mmc);
bc897b1d
LW		 2957 if (err)
2958 mmc->has_init = 0;
2959 else
2960 mmc->has_init = 1;
e9550449
CLC		 2961 return err;
2962}
2963
2964int mmc_init(struct mmc *mmc)
2965{
bd47c135 2966 int err = 0;
36332b6e 2967 __maybe_unused ulong start;
c4d660d4 2968#if CONFIG_IS_ENABLED(DM_MMC)
33fb211d 2969 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
e9550449 2970
33fb211d
SG		 2971 upriv->mmc = mmc;
2972#endif
e9550449
CLC		 2973 if (mmc->has_init)
2974 return 0;
d803fea5
MZ		 2975
2976 start = get_timer(0);
2977
e9550449
CLC		 2978 if (!mmc->init_in_progress)
2979 err = mmc_start_init(mmc);
2980
bd47c135 2981 if (!err)
e9550449 2982 err = mmc_complete_init(mmc);
919b4858 2983 if (err)
d4d64889 2984 pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
919b4858 2985
bc897b1d 2986 return err;
272cc70b
AF		 2987}
2988
fceea992
MV		 2989#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
2990 CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
2991 CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
2992int mmc_deinit(struct mmc *mmc)
2993{
2994 u32 caps_filtered;
2995
2996 if (!mmc->has_init)
2997 return 0;
2998
2999 if (IS_SD(mmc)) {
3000 caps_filtered = mmc->card_caps &
3001 ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
3002 MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
3003 MMC_CAP(UHS_SDR104));
3004
3005 return sd_select_mode_and_width(mmc, caps_filtered);
3006 } else {
3007 caps_filtered = mmc->card_caps &
fb8c2e8f 3008 ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400) | MMC_CAP(MMC_HS_400_ES));
fceea992
MV		 3009
3010 return mmc_select_mode_and_width(mmc, caps_filtered);
3011 }
3012}
3013#endif
3014
ab71188c
MN		 3015int mmc_set_dsr(struct mmc *mmc, u16 val)
3016{
3017 mmc->dsr = val;
3018 return 0;
3019}
3020
cee9ab7c 3021/* CPU-specific MMC initializations */
b75d8dc5 3022__weak int cpu_mmc_init(struct bd_info *bis)
272cc70b
AF		 3023{
3024 return -1;
3025}
3026
cee9ab7c 3027/* board-specific MMC initializations. */
b75d8dc5 3028__weak int board_mmc_init(struct bd_info *bis)
cee9ab7c
JH		 3029{
3030 return -1;
3031}
272cc70b 3032
e9550449
CLC		 3033void mmc_set_preinit(struct mmc *mmc, int preinit)
3034{
3035 mmc->preinit = preinit;
3036}
3037
8a856db2 3038#if CONFIG_IS_ENABLED(DM_MMC)
b75d8dc5 3039static int mmc_probe(struct bd_info *bis)
8e3332e2 3040{
4a1db6d8 3041 int ret, i;
8e3332e2 3042 struct uclass *uc;
4a1db6d8 3043 struct udevice *dev;
8e3332e2
SS		 3044
3045 ret = uclass_get(UCLASS_MMC, &uc);
3046 if (ret)
3047 return ret;
3048
4a1db6d8
SG		 3049 /*
3050 * Try to add them in sequence order. Really with driver model we
3051 * should allow holes, but the current MMC list does not allow that.
3052 * So if we request 0, 1, 3 we will get 0, 1, 2.
3053 */
3054 for (i = 0; ; i++) {
3055 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
3056 if (ret == -ENODEV)
3057 break;
3058 }
3059 uclass_foreach_dev(dev, uc) {
3060 ret = device_probe(dev);
8e3332e2 3061 if (ret)
d8e3d420 3062 pr_err("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 3063 }
3064
3065 return 0;
3066}
3067#else
b75d8dc5 3068static int mmc_probe(struct bd_info *bis)
8e3332e2
SS		 3069{
3070 if (board_mmc_init(bis) < 0)
3071 cpu_mmc_init(bis);
3072
3073 return 0;
3074}
3075#endif
e9550449 3076
b75d8dc5 3077int mmc_initialize(struct bd_info *bis)
272cc70b 3078{
1b26bab1 3079 static int initialized = 0;
8e3332e2 3080 int ret;
1b26bab1
DK		 3081 if (initialized) /* Avoid initializing mmc multiple times */
3082 return 0;
3083 initialized = 1;
3084
c4d660d4 3085#if !CONFIG_IS_ENABLED(BLK)
b5b838f1 3086#if !CONFIG_IS_ENABLED(MMC_TINY)
c40fdca6 3087 mmc_list_init();
b5b838f1 3088#endif
c40fdca6 3089#endif
8e3332e2
SS		 3090 ret = mmc_probe(bis);
3091 if (ret)
3092 return ret;
272cc70b 3093
bb0dc108 3094#ifndef CONFIG_SPL_BUILD
272cc70b 3095 print_mmc_devices(',');
bb0dc108 3096#endif
272cc70b 3097
c40fdca6 3098 mmc_do_preinit();
272cc70b
AF		 3099 return 0;
3100}
cd3d4880 3101
80f02019
LV		 3102#if CONFIG_IS_ENABLED(DM_MMC)
3103int mmc_init_device(int num)
3104{
3105 struct udevice *dev;
3106 struct mmc *m;
3107 int ret;
3108
2153a08a
AG		 3109 if (uclass_get_device_by_seq(UCLASS_MMC, num, &dev)) {
3110 ret = uclass_get_device(UCLASS_MMC, num, &dev);
3111 if (ret)
3112 return ret;
3113 }
80f02019
LV		 3114
3115 m = mmc_get_mmc_dev(dev);
3116 if (!m)
3117 return 0;
337af54a
VYA		 3118
3119 /* Initialising user set speed mode */
3120 m->user_speed_mode = MMC_MODES_END;
3121
80f02019
LV		 3122 if (m->preinit)
3123 mmc_start_init(m);
3124
3125 return 0;
3126}
3127#endif
3128
cd3d4880 3129#ifdef CONFIG_CMD_BKOPS_ENABLE
cf1f7355 3130int mmc_set_bkops_enable(struct mmc *mmc, bool autobkops, bool enable)
cd3d4880
TM		 3131{
3132 int err;
cf1f7355 3133 u32 bit = autobkops ? BIT(1) : BIT(0);
cd3d4880
TM		 3134 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
3135
3136 err = mmc_send_ext_csd(mmc, ext_csd);
3137 if (err) {
3138 puts("Could not get ext_csd register values\n");
3139 return err;
3140 }
3141
3142 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
3143 puts("Background operations not supported on device\n");
3144 return -EMEDIUMTYPE;
3145 }
3146
cf1f7355 3147 if (enable && (ext_csd[EXT_CSD_BKOPS_EN] & bit)) {
cd3d4880
TM		 3148 puts("Background operations already enabled\n");
3149 return 0;
3150 }
3151
cf1f7355
MV		 3152 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN,
3153 enable ? bit : 0);
cd3d4880 3154 if (err) {
cf1f7355
MV		 3155 printf("Failed to %sable manual background operations\n",
3156 enable ? "en" : "dis");
cd3d4880
TM		 3157 return err;
3158 }
3159
cf1f7355
MV		 3160 printf("%sabled %s background operations\n",
3161 enable ? "En" : "Dis", autobkops ? "auto" : "manual");
cd3d4880
TM		 3162
3163 return 0;
3164}
3165#endif
4dee3f78
DW		 3166
3167__weak int mmc_get_env_dev(void)
3168{
3169#ifdef CONFIG_SYS_MMC_ENV_DEV
3170 return CONFIG_SYS_MMC_ENV_DEV;
3171#else
3172 return 0;
3173#endif
3174}
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