[J-u-boot.git] / drivers / mmc / dw_mmc.c

/*
 * (C) Copyright 2012 SAMSUNG Electronics
 * Jaehoon Chung <[email protected]>
 * Rajeshawari Shinde <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <bouncebuf.h>
#include <common.h>
#include <errno.h>
#include <malloc.h>
#include <memalign.h>
#include <mmc.h>
#include <dwmmc.h>

#define PAGE_SIZE 4096

static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
{
	unsigned long timeout = 1000;
	u32 ctrl;

	dwmci_writel(host, DWMCI_CTRL, value);

	while (timeout--) {
		ctrl = dwmci_readl(host, DWMCI_CTRL);
		if (!(ctrl & DWMCI_RESET_ALL))
			return 1;
	}
	return 0;
}

static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
		u32 desc0, u32 desc1, u32 desc2)
{
	struct dwmci_idmac *desc = idmac;

	desc->flags = desc0;
	desc->cnt = desc1;
	desc->addr = desc2;
	desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
}

static void dwmci_prepare_data(struct dwmci_host *host,
			       struct mmc_data *data,
			       struct dwmci_idmac *cur_idmac,
			       void *bounce_buffer)
{
	unsigned long ctrl;
	unsigned int i = 0, flags, cnt, blk_cnt;
	ulong data_start, data_end;


	blk_cnt = data->blocks;

	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);

	data_start = (ulong)cur_idmac;
	dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);

	do {
		flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
		flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
		if (blk_cnt <= 8) {
			flags |= DWMCI_IDMAC_LD;
			cnt = data->blocksize * blk_cnt;
		} else
			cnt = data->blocksize * 8;

		dwmci_set_idma_desc(cur_idmac, flags, cnt,
				    (ulong)bounce_buffer + (i * PAGE_SIZE));

		if (blk_cnt <= 8)
			break;
		blk_cnt -= 8;
		cur_idmac++;
		i++;
	} while(1);

	data_end = (ulong)cur_idmac;
	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);

	ctrl = dwmci_readl(host, DWMCI_CTRL);
	ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
	dwmci_writel(host, DWMCI_CTRL, ctrl);

	ctrl = dwmci_readl(host, DWMCI_BMOD);
	ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
	dwmci_writel(host, DWMCI_BMOD, ctrl);

	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
}

static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
{
	int ret = 0;
	u32 timeout = 240000;
	u32 mask, size, i, len = 0;
	u32 *buf = NULL;
	ulong start = get_timer(0);
	u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
			    RX_WMARK_SHIFT) + 1) * 2;

	size = data->blocksize * data->blocks / 4;
	if (data->flags == MMC_DATA_READ)
		buf = (unsigned int *)data->dest;
	else
		buf = (unsigned int *)data->src;

	for (;;) {
		mask = dwmci_readl(host, DWMCI_RINTSTS);
		/* Error during data transfer. */
		if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
			debug("%s: DATA ERROR!\n", __func__);
			ret = -EINVAL;
			break;
		}

		if (host->fifo_mode && size) {
			len = 0;
			if (data->flags == MMC_DATA_READ &&
			    (mask & DWMCI_INTMSK_RXDR)) {
				while (size) {
					len = dwmci_readl(host, DWMCI_STATUS);
					len = (len >> DWMCI_FIFO_SHIFT) &
						    DWMCI_FIFO_MASK;
					len = min(size, len);
					for (i = 0; i < len; i++)
						*buf++ =
						dwmci_readl(host, DWMCI_DATA);
					size = size > len ? (size - len) : 0;
				}
				dwmci_writel(host, DWMCI_RINTSTS,
					     DWMCI_INTMSK_RXDR);
			} else if (data->flags == MMC_DATA_WRITE &&
				   (mask & DWMCI_INTMSK_TXDR)) {
				while (size) {
					len = dwmci_readl(host, DWMCI_STATUS);
					len = fifo_depth - ((len >>
						   DWMCI_FIFO_SHIFT) &
						   DWMCI_FIFO_MASK);
					len = min(size, len);
					for (i = 0; i < len; i++)
						dwmci_writel(host, DWMCI_DATA,
							     *buf++);
					size = size > len ? (size - len) : 0;
				}
				dwmci_writel(host, DWMCI_RINTSTS,
					     DWMCI_INTMSK_TXDR);
			}
		}

		/* Data arrived correctly. */
		if (mask & DWMCI_INTMSK_DTO) {
			ret = 0;
			break;
		}

		/* Check for timeout. */
		if (get_timer(start) > timeout) {
			debug("%s: Timeout waiting for data!\n",
			      __func__);
			ret = -ETIMEDOUT;
			break;
		}
	}

	dwmci_writel(host, DWMCI_RINTSTS, mask);

	return ret;
}

static int dwmci_set_transfer_mode(struct dwmci_host *host,
		struct mmc_data *data)
{
	unsigned long mode;

	mode = DWMCI_CMD_DATA_EXP;
	if (data->flags & MMC_DATA_WRITE)
		mode |= DWMCI_CMD_RW;

	return mode;
}

#ifdef CONFIG_DM_MMC_OPS
static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
		   struct mmc_data *data)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
		struct mmc_data *data)
{
#endif
	struct dwmci_host *host = mmc->priv;
	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
				 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
	int ret = 0, flags = 0, i;
	unsigned int timeout = 500;
	u32 retry = 100000;
	u32 mask, ctrl;
	ulong start = get_timer(0);
	struct bounce_buffer bbstate;

	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
		if (get_timer(start) > timeout) {
			debug("%s: Timeout on data busy\n", __func__);
			return -ETIMEDOUT;
		}
	}

	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);

	if (data) {
		if (host->fifo_mode) {
			dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
			dwmci_writel(host, DWMCI_BYTCNT,
				     data->blocksize * data->blocks);
			dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
		} else {
			if (data->flags == MMC_DATA_READ) {
				bounce_buffer_start(&bbstate, (void*)data->dest,
						data->blocksize *
						data->blocks, GEN_BB_WRITE);
			} else {
				bounce_buffer_start(&bbstate, (void*)data->src,
						data->blocksize *
						data->blocks, GEN_BB_READ);
			}
			dwmci_prepare_data(host, data, cur_idmac,
					   bbstate.bounce_buffer);
		}
	}

	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);

	if (data)
		flags = dwmci_set_transfer_mode(host, data);

	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
		return -1;

	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
		flags |= DWMCI_CMD_ABORT_STOP;
	else
		flags |= DWMCI_CMD_PRV_DAT_WAIT;

	if (cmd->resp_type & MMC_RSP_PRESENT) {
		flags |= DWMCI_CMD_RESP_EXP;
		if (cmd->resp_type & MMC_RSP_136)
			flags |= DWMCI_CMD_RESP_LENGTH;
	}

	if (cmd->resp_type & MMC_RSP_CRC)
		flags |= DWMCI_CMD_CHECK_CRC;

	flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);

	debug("Sending CMD%d\n",cmd->cmdidx);

	dwmci_writel(host, DWMCI_CMD, flags);

	for (i = 0; i < retry; i++) {
		mask = dwmci_readl(host, DWMCI_RINTSTS);
		if (mask & DWMCI_INTMSK_CDONE) {
			if (!data)
				dwmci_writel(host, DWMCI_RINTSTS, mask);
			break;
		}
	}

	if (i == retry) {
		debug("%s: Timeout.\n", __func__);
		return -ETIMEDOUT;
	}

	if (mask & DWMCI_INTMSK_RTO) {
		/*
		 * Timeout here is not necessarily fatal. (e)MMC cards
		 * will splat here when they receive CMD55 as they do
		 * not support this command and that is exactly the way
		 * to tell them apart from SD cards. Thus, this output
		 * below shall be debug(). eMMC cards also do not favor
		 * CMD8, please keep that in mind.
		 */
		debug("%s: Response Timeout.\n", __func__);
		return -ETIMEDOUT;
	} else if (mask & DWMCI_INTMSK_RE) {
		debug("%s: Response Error.\n", __func__);
		return -EIO;
	}


	if (cmd->resp_type & MMC_RSP_PRESENT) {
		if (cmd->resp_type & MMC_RSP_136) {
			cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
			cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
			cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
			cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
		} else {
			cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
		}
	}

	if (data) {
		ret = dwmci_data_transfer(host, data);

		/* only dma mode need it */
		if (!host->fifo_mode) {
			ctrl = dwmci_readl(host, DWMCI_CTRL);
			ctrl &= ~(DWMCI_DMA_EN);
			dwmci_writel(host, DWMCI_CTRL, ctrl);
			bounce_buffer_stop(&bbstate);
		}
	}

	udelay(100);

	return ret;
}

static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
{
	u32 div, status;
	int timeout = 10000;
	unsigned long sclk;

	if ((freq == host->clock) || (freq == 0))
		return 0;
	/*
	 * If host->get_mmc_clk isn't defined,
	 * then assume that host->bus_hz is source clock value.
	 * host->bus_hz should be set by user.
	 */
	if (host->get_mmc_clk)
		sclk = host->get_mmc_clk(host, freq);
	else if (host->bus_hz)
		sclk = host->bus_hz;
	else {
		debug("%s: Didn't get source clock value.\n", __func__);
		return -EINVAL;
	}

	if (sclk == freq)
		div = 0;	/* bypass mode */
	else
		div = DIV_ROUND_UP(sclk, 2 * freq);

	dwmci_writel(host, DWMCI_CLKENA, 0);
	dwmci_writel(host, DWMCI_CLKSRC, 0);

	dwmci_writel(host, DWMCI_CLKDIV, div);
	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);

	do {
		status = dwmci_readl(host, DWMCI_CMD);
		if (timeout-- < 0) {
			debug("%s: Timeout!\n", __func__);
			return -ETIMEDOUT;
		}
	} while (status & DWMCI_CMD_START);

	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
			DWMCI_CLKEN_LOW_PWR);

	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
			DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);

	timeout = 10000;
	do {
		status = dwmci_readl(host, DWMCI_CMD);
		if (timeout-- < 0) {
			debug("%s: Timeout!\n", __func__);
			return -ETIMEDOUT;
		}
	} while (status & DWMCI_CMD_START);

	host->clock = freq;

	return 0;
}

#ifdef CONFIG_DM_MMC_OPS
static int dwmci_set_ios(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
#else
static int dwmci_set_ios(struct mmc *mmc)
{
#endif
	struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
	u32 ctype, regs;

	debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);

	dwmci_setup_bus(host, mmc->clock);
	switch (mmc->bus_width) {
	case 8:
		ctype = DWMCI_CTYPE_8BIT;
		break;
	case 4:
		ctype = DWMCI_CTYPE_4BIT;
		break;
	default:
		ctype = DWMCI_CTYPE_1BIT;
		break;
	}

	dwmci_writel(host, DWMCI_CTYPE, ctype);

	regs = dwmci_readl(host, DWMCI_UHS_REG);
	if (mmc->ddr_mode)
		regs |= DWMCI_DDR_MODE;
	else
		regs &= ~DWMCI_DDR_MODE;

	dwmci_writel(host, DWMCI_UHS_REG, regs);

	if (host->clksel)
		host->clksel(host);

	return 0;
}

static int dwmci_init(struct mmc *mmc)
{
	struct dwmci_host *host = mmc->priv;

	if (host->board_init)
		host->board_init(host);

	dwmci_writel(host, DWMCI_PWREN, 1);

	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
		debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
		return -EIO;
	}

	/* Enumerate at 400KHz */
	dwmci_setup_bus(host, mmc->cfg->f_min);

	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
	dwmci_writel(host, DWMCI_INTMASK, 0);

	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);

	dwmci_writel(host, DWMCI_IDINTEN, 0);
	dwmci_writel(host, DWMCI_BMOD, 1);

	if (!host->fifoth_val) {
		uint32_t fifo_size;

		fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
		fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
		host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
				TX_WMARK(fifo_size / 2);
	}
	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);

	dwmci_writel(host, DWMCI_CLKENA, 0);
	dwmci_writel(host, DWMCI_CLKSRC, 0);

	return 0;
}

#ifdef CONFIG_DM_MMC_OPS
int dwmci_probe(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);

	return dwmci_init(mmc);
}

const struct dm_mmc_ops dm_dwmci_ops = {
	.send_cmd	= dwmci_send_cmd,
	.set_ios	= dwmci_set_ios,
};

#else
static const struct mmc_ops dwmci_ops = {
	.send_cmd	= dwmci_send_cmd,
	.set_ios	= dwmci_set_ios,
	.init		= dwmci_init,
};
#endif

void dwmci_setup_cfg(struct mmc_config *cfg, struct dwmci_host *host,
		u32 max_clk, u32 min_clk)
{
	cfg->name = host->name;
#ifndef CONFIG_DM_MMC_OPS
	cfg->ops = &dwmci_ops;
#endif
	cfg->f_min = min_clk;
	cfg->f_max = max_clk;

	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;

	cfg->host_caps = host->caps;

	if (host->buswidth == 8) {
		cfg->host_caps |= MMC_MODE_8BIT;
		cfg->host_caps &= ~MMC_MODE_4BIT;
	} else {
		cfg->host_caps |= MMC_MODE_4BIT;
		cfg->host_caps &= ~MMC_MODE_8BIT;
	}
	cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;

	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
}

#ifdef CONFIG_BLK
int dwmci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
{
	return mmc_bind(dev, mmc, cfg);
}
#else
int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
{
	dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);

	host->mmc = mmc_create(&host->cfg, host);
	if (host->mmc == NULL)
		return -1;

	return 0;
}
#endif
Commit	Line	Data
757bff49 JC	1	/*
	2	* (C) Copyright 2012 SAMSUNG Electronics
	3	* Jaehoon Chung <[email protected]>
	4	* Rajeshawari Shinde <[email protected]>
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
757bff49 JC	7	*/
757bff49 JC	8
2a7a210e	9	#include <bouncebuf.h>
757bff49	10	#include <common.h>
1c87ffe8	11	#include <errno.h>
757bff49	12	#include <malloc.h>
cf92e05c	13	#include <memalign.h>
757bff49 JC	14	#include <mmc.h>
757bff49 JC	15	#include <dwmmc.h>
757bff49 JC	16
	17	#define PAGE_SIZE 4096
	18
	19	static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
	20	{
	21	unsigned long timeout = 1000;
	22	u32 ctrl;
	23
	24	dwmci_writel(host, DWMCI_CTRL, value);
	25
	26	while (timeout--) {
	27	ctrl = dwmci_readl(host, DWMCI_CTRL);
	28	if (!(ctrl & DWMCI_RESET_ALL))
	29	return 1;
	30	}
	31	return 0;
	32	}
	33
	34	static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
	35	u32 desc0, u32 desc1, u32 desc2)
	36	{
	37	struct dwmci_idmac *desc = idmac;
	38
	39	desc->flags = desc0;
	40	desc->cnt = desc1;
	41	desc->addr = desc2;
41f7be3c	42	desc->next_addr = (ulong)desc + sizeof(struct dwmci_idmac);
757bff49 JC	43	}
	44
	45	static void dwmci_prepare_data(struct dwmci_host *host,
2a7a210e AB	46	struct mmc_data *data,
	47	struct dwmci_idmac *cur_idmac,
	48	void *bounce_buffer)
757bff49 JC	49	{
	50	unsigned long ctrl;
	51	unsigned int i = 0, flags, cnt, blk_cnt;
2a7a210e	52	ulong data_start, data_end;
757bff49 JC	53
	54
	55	blk_cnt = data->blocks;
	56
	57	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
	58
	59	data_start = (ulong)cur_idmac;
41f7be3c	60	dwmci_writel(host, DWMCI_DBADDR, (ulong)cur_idmac);
757bff49	61
757bff49 JC	62	do {
	63	flags = DWMCI_IDMAC_OWN \| DWMCI_IDMAC_CH ;
	64	flags \|= (i == 0) ? DWMCI_IDMAC_FS : 0;
	65	if (blk_cnt <= 8) {
	66	flags \|= DWMCI_IDMAC_LD;
	67	cnt = data->blocksize * blk_cnt;
	68	} else
	69	cnt = data->blocksize * 8;
	70
	71	dwmci_set_idma_desc(cur_idmac, flags, cnt,
41f7be3c	72	(ulong)bounce_buffer + (i * PAGE_SIZE));
757bff49	73
21bd5761	74	if (blk_cnt <= 8)
757bff49 JC	75	break;
	76	blk_cnt -= 8;
	77	cur_idmac++;
	78	i++;
	79	} while(1);
	80
	81	data_end = (ulong)cur_idmac;
	82	flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
	83
	84	ctrl = dwmci_readl(host, DWMCI_CTRL);
	85	ctrl \|= DWMCI_IDMAC_EN \| DWMCI_DMA_EN;
	86	dwmci_writel(host, DWMCI_CTRL, ctrl);
	87
	88	ctrl = dwmci_readl(host, DWMCI_BMOD);
	89	ctrl \|= DWMCI_BMOD_IDMAC_FB \| DWMCI_BMOD_IDMAC_EN;
	90	dwmci_writel(host, DWMCI_BMOD, ctrl);
	91
	92	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	93	dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
	94	}
	95
a65f51b9	96	static int dwmci_data_transfer(struct dwmci_host host, struct mmc_data data)
f382eb83	97	{
f382eb83	98	int ret = 0;
a65f51b9	99	u32 timeout = 240000;
	100	u32 mask, size, i, len = 0;
	101	u32 *buf = NULL;
f382eb83	102	ulong start = get_timer(0);
a65f51b9	103	u32 fifo_depth = (((host->fifoth_val & RX_WMARK_MASK) >>
	104	RX_WMARK_SHIFT) + 1) * 2;
	105
	106	size = data->blocksize * data->blocks / 4;
	107	if (data->flags == MMC_DATA_READ)
	108	buf = (unsigned int *)data->dest;
	109	else
	110	buf = (unsigned int *)data->src;
f382eb83	111
	112	for (;;) {
	113	mask = dwmci_readl(host, DWMCI_RINTSTS);
	114	/* Error during data transfer. */
	115	if (mask & (DWMCI_DATA_ERR \| DWMCI_DATA_TOUT)) {
	116	debug("%s: DATA ERROR!\n", __func__);
	117	ret = -EINVAL;
	118	break;
	119	}
	120
a65f51b9	121	if (host->fifo_mode && size) {
720724d0	122	len = 0;
2b429033 JC	123	if (data->flags == MMC_DATA_READ &&
	124	(mask & DWMCI_INTMSK_RXDR)) {
	125	while (size) {
a65f51b9	126	len = dwmci_readl(host, DWMCI_STATUS);
	127	len = (len >> DWMCI_FIFO_SHIFT) &
	128	DWMCI_FIFO_MASK;
2990e07a	129	len = min(size, len);
a65f51b9	130	for (i = 0; i < len; i++)
	131	*buf++ =
	132	dwmci_readl(host, DWMCI_DATA);
2b429033	133	size = size > len ? (size - len) : 0;
a65f51b9	134	}
2b429033 JC	135	dwmci_writel(host, DWMCI_RINTSTS,
	136	DWMCI_INTMSK_RXDR);
	137	} else if (data->flags == MMC_DATA_WRITE &&
	138	(mask & DWMCI_INTMSK_TXDR)) {
	139	while (size) {
a65f51b9	140	len = dwmci_readl(host, DWMCI_STATUS);
	141	len = fifo_depth - ((len >>
	142	DWMCI_FIFO_SHIFT) &
	143	DWMCI_FIFO_MASK);
2990e07a	144	len = min(size, len);
a65f51b9	145	for (i = 0; i < len; i++)
	146	dwmci_writel(host, DWMCI_DATA,
	147	*buf++);
2b429033	148	size = size > len ? (size - len) : 0;
a65f51b9	149	}
2b429033 JC	150	dwmci_writel(host, DWMCI_RINTSTS,
2b429033 JC	151	DWMCI_INTMSK_TXDR);
a65f51b9	152	}
a65f51b9	153	}
a65f51b9	154
f382eb83	155	/* Data arrived correctly. */
	156	if (mask & DWMCI_INTMSK_DTO) {
	157	ret = 0;
	158	break;
	159	}
	160
	161	/* Check for timeout. */
	162	if (get_timer(start) > timeout) {
	163	debug("%s: Timeout waiting for data!\n",
	164	__func__);
915ffa52	165	ret = -ETIMEDOUT;
f382eb83	166	break;
	167	}
	168	}
	169
	170	dwmci_writel(host, DWMCI_RINTSTS, mask);
	171
	172	return ret;
	173	}
	174
757bff49 JC	175	static int dwmci_set_transfer_mode(struct dwmci_host *host,
	176	struct mmc_data *data)
	177	{
	178	unsigned long mode;
	179
	180	mode = DWMCI_CMD_DATA_EXP;
	181	if (data->flags & MMC_DATA_WRITE)
	182	mode \|= DWMCI_CMD_RW;
	183
	184	return mode;
	185	}
	186
691272fe	187	#ifdef CONFIG_DM_MMC_OPS
5628347f	188	static int dwmci_send_cmd(struct udevice dev, struct mmc_cmd cmd,
691272fe SG	189	struct mmc_data *data)
	190	{
	191	struct mmc *mmc = mmc_get_mmc_dev(dev);
	192	#else
757bff49 JC	193	static int dwmci_send_cmd(struct mmc mmc, struct mmc_cmd cmd,
	194	struct mmc_data *data)
	195	{
691272fe	196	#endif
93bfd616	197	struct dwmci_host *host = mmc->priv;
2136d226	198	ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
21bd5761	199	data ? DIV_ROUND_UP(data->blocks, 8) : 0);
9042d974	200	int ret = 0, flags = 0, i;
02ebd42c	201	unsigned int timeout = 500;
9b5b8b6e	202	u32 retry = 100000;
757bff49	203	u32 mask, ctrl;
9c50e35f	204	ulong start = get_timer(0);
2a7a210e	205	struct bounce_buffer bbstate;
757bff49 JC	206
757bff49 JC	207	while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
9c50e35f	208	if (get_timer(start) > timeout) {
1c87ffe8	209	debug("%s: Timeout on data busy\n", __func__);
915ffa52	210	return -ETIMEDOUT;
757bff49	211	}
757bff49 JC	212	}
	213
	214	dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
	215
2a7a210e	216	if (data) {
a65f51b9	217	if (host->fifo_mode) {
	218	dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
	219	dwmci_writel(host, DWMCI_BYTCNT,
	220	data->blocksize * data->blocks);
	221	dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
2a7a210e	222	} else {
a65f51b9	223	if (data->flags == MMC_DATA_READ) {
	224	bounce_buffer_start(&bbstate, (void*)data->dest,
	225	data->blocksize *
	226	data->blocks, GEN_BB_WRITE);
	227	} else {
	228	bounce_buffer_start(&bbstate, (void*)data->src,
	229	data->blocksize *
	230	data->blocks, GEN_BB_READ);
	231	}
	232	dwmci_prepare_data(host, data, cur_idmac,
	233	bbstate.bounce_buffer);
2a7a210e	234	}
2a7a210e	235	}
757bff49	236
757bff49 JC	237	dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
	238
	239	if (data)
	240	flags = dwmci_set_transfer_mode(host, data);
	241
	242	if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
	243	return -1;
	244
	245	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
	246	flags \|= DWMCI_CMD_ABORT_STOP;
	247	else
	248	flags \|= DWMCI_CMD_PRV_DAT_WAIT;
	249
	250	if (cmd->resp_type & MMC_RSP_PRESENT) {
	251	flags \|= DWMCI_CMD_RESP_EXP;
	252	if (cmd->resp_type & MMC_RSP_136)
	253	flags \|= DWMCI_CMD_RESP_LENGTH;
	254	}
	255
	256	if (cmd->resp_type & MMC_RSP_CRC)
	257	flags \|= DWMCI_CMD_CHECK_CRC;
	258
	259	flags \|= (cmd->cmdidx \| DWMCI_CMD_START \| DWMCI_CMD_USE_HOLD_REG);
	260
	261	debug("Sending CMD%d\n",cmd->cmdidx);
	262
	263	dwmci_writel(host, DWMCI_CMD, flags);
	264
	265	for (i = 0; i < retry; i++) {
	266	mask = dwmci_readl(host, DWMCI_RINTSTS);
	267	if (mask & DWMCI_INTMSK_CDONE) {
	268	if (!data)
	269	dwmci_writel(host, DWMCI_RINTSTS, mask);
	270	break;
	271	}
	272	}
	273
f33c9305	274	if (i == retry) {
1c87ffe8	275	debug("%s: Timeout.\n", __func__);
915ffa52	276	return -ETIMEDOUT;
f33c9305	277	}
757bff49 JC	278
757bff49 JC	279	if (mask & DWMCI_INTMSK_RTO) {
f33c9305 PM	280	/*
	281	* Timeout here is not necessarily fatal. (e)MMC cards
	282	* will splat here when they receive CMD55 as they do
	283	* not support this command and that is exactly the way
	284	* to tell them apart from SD cards. Thus, this output
	285	* below shall be debug(). eMMC cards also do not favor
	286	* CMD8, please keep that in mind.
	287	*/
	288	debug("%s: Response Timeout.\n", __func__);
915ffa52	289	return -ETIMEDOUT;
757bff49	290	} else if (mask & DWMCI_INTMSK_RE) {
1c87ffe8 SG	291	debug("%s: Response Error.\n", __func__);
1c87ffe8 SG	292	return -EIO;
757bff49 JC	293	}
	294
	295
	296	if (cmd->resp_type & MMC_RSP_PRESENT) {
	297	if (cmd->resp_type & MMC_RSP_136) {
	298	cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
	299	cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
	300	cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
	301	cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
	302	} else {
	303	cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
	304	}
	305	}
	306
	307	if (data) {
a65f51b9	308	ret = dwmci_data_transfer(host, data);
	309
	310	/* only dma mode need it */
	311	if (!host->fifo_mode) {
	312	ctrl = dwmci_readl(host, DWMCI_CTRL);
	313	ctrl &= ~(DWMCI_DMA_EN);
	314	dwmci_writel(host, DWMCI_CTRL, ctrl);
	315	bounce_buffer_stop(&bbstate);
	316	}
757bff49 JC	317	}
	318
	319	udelay(100);
	320
9042d974	321	return ret;
757bff49 JC	322	}
	323
	324	static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
	325	{
	326	u32 div, status;
	327	int timeout = 10000;
	328	unsigned long sclk;
	329
9c50e35f	330	if ((freq == host->clock) \|\| (freq == 0))
757bff49	331	return 0;
757bff49	332	/*
f33c9305	333	* If host->get_mmc_clk isn't defined,
757bff49	334	* then assume that host->bus_hz is source clock value.
f33c9305	335	* host->bus_hz should be set by user.
757bff49	336	*/
b44fe83a	337	if (host->get_mmc_clk)
e3563f2e	338	sclk = host->get_mmc_clk(host, freq);
757bff49 JC	339	else if (host->bus_hz)
	340	sclk = host->bus_hz;
	341	else {
1c87ffe8	342	debug("%s: Didn't get source clock value.\n", __func__);
757bff49 JC	343	return -EINVAL;
	344	}
	345
6ace153d CLS	346	if (sclk == freq)
	347	div = 0; /* bypass mode */
	348	else
	349	div = DIV_ROUND_UP(sclk, 2 * freq);
757bff49 JC	350
	351	dwmci_writel(host, DWMCI_CLKENA, 0);
	352	dwmci_writel(host, DWMCI_CLKSRC, 0);
	353
	354	dwmci_writel(host, DWMCI_CLKDIV, div);
	355	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
	356	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
	357
	358	do {
	359	status = dwmci_readl(host, DWMCI_CMD);
	360	if (timeout-- < 0) {
1c87ffe8	361	debug("%s: Timeout!\n", __func__);
757bff49 JC	362	return -ETIMEDOUT;
	363	}
	364	} while (status & DWMCI_CMD_START);
	365
	366	dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE \|
	367	DWMCI_CLKEN_LOW_PWR);
	368
	369	dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT \|
	370	DWMCI_CMD_UPD_CLK \| DWMCI_CMD_START);
	371
	372	timeout = 10000;
	373	do {
	374	status = dwmci_readl(host, DWMCI_CMD);
	375	if (timeout-- < 0) {
1c87ffe8	376	debug("%s: Timeout!\n", __func__);
757bff49 JC	377	return -ETIMEDOUT;
	378	}
	379	} while (status & DWMCI_CMD_START);
	380
	381	host->clock = freq;
	382
	383	return 0;
	384	}
	385
691272fe	386	#ifdef CONFIG_DM_MMC_OPS
5628347f	387	static int dwmci_set_ios(struct udevice *dev)
691272fe SG	388	{
	389	struct mmc *mmc = mmc_get_mmc_dev(dev);
	390	#else
07b0b9c0	391	static int dwmci_set_ios(struct mmc *mmc)
757bff49	392	{
691272fe	393	#endif
045bdcd0 JC	394	struct dwmci_host host = (struct dwmci_host )mmc->priv;
045bdcd0 JC	395	u32 ctype, regs;
757bff49	396
f33c9305	397	debug("Buswidth = %d, clock: %d\n", mmc->bus_width, mmc->clock);
757bff49 JC	398
	399	dwmci_setup_bus(host, mmc->clock);
	400	switch (mmc->bus_width) {
	401	case 8:
	402	ctype = DWMCI_CTYPE_8BIT;
	403	break;
	404	case 4:
	405	ctype = DWMCI_CTYPE_4BIT;
	406	break;
	407	default:
	408	ctype = DWMCI_CTYPE_1BIT;
	409	break;
	410	}
	411
	412	dwmci_writel(host, DWMCI_CTYPE, ctype);
	413
045bdcd0	414	regs = dwmci_readl(host, DWMCI_UHS_REG);
2b8a9692	415	if (mmc->ddr_mode)
045bdcd0 JC	416	regs \|= DWMCI_DDR_MODE;
045bdcd0 JC	417	else
afc9e2b5	418	regs &= ~DWMCI_DDR_MODE;
045bdcd0 JC	419
	420	dwmci_writel(host, DWMCI_UHS_REG, regs);
	421
757bff49 JC	422	if (host->clksel)
757bff49 JC	423	host->clksel(host);
07b0b9c0	424
691272fe	425	return 0;
757bff49 JC	426	}
	427
	428	static int dwmci_init(struct mmc *mmc)
	429	{
93bfd616	430	struct dwmci_host *host = mmc->priv;
757bff49	431
18ab6755 JC	432	if (host->board_init)
18ab6755 JC	433	host->board_init(host);
6f0b7caa	434
757bff49 JC	435	dwmci_writel(host, DWMCI_PWREN, 1);
	436
	437	if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
1c87ffe8 SG	438	debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
1c87ffe8 SG	439	return -EIO;
757bff49 JC	440	}
757bff49 JC	441
9c50e35f	442	/* Enumerate at 400KHz */
93bfd616	443	dwmci_setup_bus(host, mmc->cfg->f_min);
9c50e35f	444
757bff49 JC	445	dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
	446	dwmci_writel(host, DWMCI_INTMASK, 0);
	447
	448	dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
	449
	450	dwmci_writel(host, DWMCI_IDINTEN, 0);
	451	dwmci_writel(host, DWMCI_BMOD, 1);
	452
760177df SG	453	if (!host->fifoth_val) {
	454	uint32_t fifo_size;
	455
	456	fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
	457	fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
	458	host->fifoth_val = MSIZE(0x2) \| RX_WMARK(fifo_size / 2 - 1) \|
	459	TX_WMARK(fifo_size / 2);
9c50e35f	460	}
760177df	461	dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
757bff49 JC	462
	463	dwmci_writel(host, DWMCI_CLKENA, 0);
	464	dwmci_writel(host, DWMCI_CLKSRC, 0);
	465
	466	return 0;
	467	}
	468
691272fe SG	469	#ifdef CONFIG_DM_MMC_OPS
	470	int dwmci_probe(struct udevice *dev)
	471	{
	472	struct mmc *mmc = mmc_get_mmc_dev(dev);
	473
	474	return dwmci_init(mmc);
	475	}
	476
	477	const struct dm_mmc_ops dm_dwmci_ops = {
	478	.send_cmd = dwmci_send_cmd,
	479	.set_ios = dwmci_set_ios,
	480	};
	481
	482	#else
ab769f22 PA	483	static const struct mmc_ops dwmci_ops = {
	484	.send_cmd = dwmci_send_cmd,
	485	.set_ios = dwmci_set_ios,
	486	.init = dwmci_init,
	487	};
691272fe	488	#endif
ab769f22	489
e5113c33 JC	490	void dwmci_setup_cfg(struct mmc_config cfg, struct dwmci_host host,
e5113c33 JC	491	u32 max_clk, u32 min_clk)
757bff49	492	{
e5113c33	493	cfg->name = host->name;
691272fe	494	#ifndef CONFIG_DM_MMC_OPS
5e6ff810	495	cfg->ops = &dwmci_ops;
691272fe	496	#endif
5e6ff810 SG	497	cfg->f_min = min_clk;
5e6ff810 SG	498	cfg->f_max = max_clk;
757bff49	499
5e6ff810	500	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34 \| MMC_VDD_165_195;
757bff49	501
e5113c33	502	cfg->host_caps = host->caps;
757bff49	503
e5113c33	504	if (host->buswidth == 8) {
5e6ff810 SG	505	cfg->host_caps \|= MMC_MODE_8BIT;
5e6ff810 SG	506	cfg->host_caps &= ~MMC_MODE_4BIT;
757bff49	507	} else {
5e6ff810 SG	508	cfg->host_caps \|= MMC_MODE_4BIT;
5e6ff810 SG	509	cfg->host_caps &= ~MMC_MODE_8BIT;
757bff49	510	}
5e6ff810 SG	511	cfg->host_caps \|= MMC_MODE_HS \| MMC_MODE_HS_52MHz;
	512
	513	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
	514	}
93bfd616	515
5e6ff810 SG	516	#ifdef CONFIG_BLK
	517	int dwmci_bind(struct udevice dev, struct mmc mmc, struct mmc_config *cfg)
	518	{
	519	return mmc_bind(dev, mmc, cfg);
	520	}
	521	#else
	522	int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
	523	{
e5113c33	524	dwmci_setup_cfg(&host->cfg, host, max_clk, min_clk);
757bff49	525
93bfd616 PA	526	host->mmc = mmc_create(&host->cfg, host);
	527	if (host->mmc == NULL)
	528	return -1;
757bff49	529
93bfd616	530	return 0;
757bff49	531	}
5e6ff810	532	#endif