[J-u-boot.git] / drivers / net / sh_eth.h

/*
 * sh_eth.h - Driver for Renesas SuperH ethernet controller.
 *
 * Copyright (C) 2008 - 2012 Renesas Solutions Corp.
 * Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
 * Copyright (c) 2007 Carlos Munoz <[email protected]>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <netdev.h>
#include <asm/types.h>

#define SHETHER_NAME "sh_eth"

#if defined(CONFIG_SH)
/* Malloc returns addresses in the P1 area (cacheable). However we need to
   use area P2 (non-cacheable) */
#define ADDR_TO_P2(addr)	((((int)(addr) & ~0xe0000000) | 0xa0000000))

/* The ethernet controller needs to use physical addresses */
#if defined(CONFIG_SH_32BIT)
#define ADDR_TO_PHY(addr)	((((int)(addr) & ~0xe0000000) | 0x40000000))
#else
#define ADDR_TO_PHY(addr)	((int)(addr) & ~0xe0000000)
#endif
#elif defined(CONFIG_ARM)
#ifndef inl
#define inl	readl
#define outl	writel
#endif
#define ADDR_TO_PHY(addr)	((int)(addr))
#define ADDR_TO_P2(addr)	(addr)
#endif /* defined(CONFIG_SH) */

/* base padding size is 16 */
#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
#endif

/* Number of supported ports */
#define MAX_PORT_NUM	2

/* Buffers must be big enough to hold the largest ethernet frame. Also, rx
   buffers must be a multiple of 32 bytes */
#define MAX_BUF_SIZE	(48 * 32)

/* The number of tx descriptors must be large enough to point to 5 or more
   frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
   We use one descriptor per frame */
#define NUM_TX_DESC		8

/* The size of the tx descriptor is determined by how much padding is used.
   4, 20, or 52 bytes of padding can be used */
#define TX_DESC_PADDING	(CONFIG_SH_ETHER_ALIGNE_SIZE - 12)

/* Tx descriptor. We always use 3 bytes of padding */
struct tx_desc_s {
	volatile u32 td0;
	u32 td1;
	u32 td2;		/* Buffer start */
	u8 padding[TX_DESC_PADDING];	/* aligned cache line size */
};

/* There is no limitation in the number of rx descriptors */
#define NUM_RX_DESC	8

/* The size of the rx descriptor is determined by how much padding is used.
   4, 20, or 52 bytes of padding can be used */
#define RX_DESC_PADDING	(CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
/* aligned cache line size */
#define RX_BUF_ALIGNE_SIZE	(CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)

/* Rx descriptor. We always use 4 bytes of padding */
struct rx_desc_s {
	volatile u32 rd0;
	volatile u32 rd1;
	u32 rd2;		/* Buffer start */
	u8 padding[TX_DESC_PADDING];	/* aligned cache line size */
};

struct sh_eth_info {
	struct tx_desc_s *tx_desc_alloc;
	struct tx_desc_s *tx_desc_base;
	struct tx_desc_s *tx_desc_cur;
	struct rx_desc_s *rx_desc_alloc;
	struct rx_desc_s *rx_desc_base;
	struct rx_desc_s *rx_desc_cur;
	u8 *rx_buf_alloc;
	u8 *rx_buf_base;
	u8 mac_addr[6];
	u8 phy_addr;
	struct eth_device *dev;
	struct phy_device *phydev;
	void __iomem *iobase;
};

struct sh_eth_dev {
	int port;
	struct sh_eth_info port_info[MAX_PORT_NUM];
};

/* from linux/drivers/net/ethernet/renesas/sh_eth.h */
enum {
	/* E-DMAC registers */
	EDSR = 0,
	EDMR,
	EDTRR,
	EDRRR,
	EESR,
	EESIPR,
	TDLAR,
	TDFAR,
	TDFXR,
	TDFFR,
	RDLAR,
	RDFAR,
	RDFXR,
	RDFFR,
	TRSCER,
	RMFCR,
	TFTR,
	FDR,
	RMCR,
	EDOCR,
	TFUCR,
	RFOCR,
	FCFTR,
	RPADIR,
	TRIMD,
	RBWAR,
	TBRAR,

	/* Ether registers */
	ECMR,
	ECSR,
	ECSIPR,
	PIR,
	PSR,
	RDMLR,
	PIPR,
	RFLR,
	IPGR,
	APR,
	MPR,
	PFTCR,
	PFRCR,
	RFCR,
	RFCF,
	TPAUSER,
	TPAUSECR,
	BCFR,
	BCFRR,
	GECMR,
	BCULR,
	MAHR,
	MALR,
	TROCR,
	CDCR,
	LCCR,
	CNDCR,
	CEFCR,
	FRECR,
	TSFRCR,
	TLFRCR,
	CERCR,
	CEECR,
	RMIIMR, /* R8A7790 */
	MAFCR,
	RTRATE,
	CSMR,
	RMII_MII,

	/* This value must be written at last. */
	SH_ETH_MAX_REGISTER_OFFSET,
};

static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
	[EDSR]	= 0x0000,
	[EDMR]	= 0x0400,
	[EDTRR]	= 0x0408,
	[EDRRR]	= 0x0410,
	[EESR]	= 0x0428,
	[EESIPR]	= 0x0430,
	[TDLAR]	= 0x0010,
	[TDFAR]	= 0x0014,
	[TDFXR]	= 0x0018,
	[TDFFR]	= 0x001c,
	[RDLAR]	= 0x0030,
	[RDFAR]	= 0x0034,
	[RDFXR]	= 0x0038,
	[RDFFR]	= 0x003c,
	[TRSCER]	= 0x0438,
	[RMFCR]	= 0x0440,
	[TFTR]	= 0x0448,
	[FDR]	= 0x0450,
	[RMCR]	= 0x0458,
	[RPADIR]	= 0x0460,
	[FCFTR]	= 0x0468,
	[CSMR] = 0x04E4,

	[ECMR]	= 0x0500,
	[ECSR]	= 0x0510,
	[ECSIPR]	= 0x0518,
	[PIR]	= 0x0520,
	[PSR]	= 0x0528,
	[PIPR]	= 0x052c,
	[RFLR]	= 0x0508,
	[APR]	= 0x0554,
	[MPR]	= 0x0558,
	[PFTCR]	= 0x055c,
	[PFRCR]	= 0x0560,
	[TPAUSER]	= 0x0564,
	[GECMR]	= 0x05b0,
	[BCULR]	= 0x05b4,
	[MAHR]	= 0x05c0,
	[MALR]	= 0x05c8,
	[TROCR]	= 0x0700,
	[CDCR]	= 0x0708,
	[LCCR]	= 0x0710,
	[CEFCR]	= 0x0740,
	[FRECR]	= 0x0748,
	[TSFRCR]	= 0x0750,
	[TLFRCR]	= 0x0758,
	[RFCR]	= 0x0760,
	[CERCR]	= 0x0768,
	[CEECR]	= 0x0770,
	[MAFCR]	= 0x0778,
	[RMII_MII] =  0x0790,
};

static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
	[ECMR]	= 0x0100,
	[RFLR]	= 0x0108,
	[ECSR]	= 0x0110,
	[ECSIPR]	= 0x0118,
	[PIR]	= 0x0120,
	[PSR]	= 0x0128,
	[RDMLR]	= 0x0140,
	[IPGR]	= 0x0150,
	[APR]	= 0x0154,
	[MPR]	= 0x0158,
	[TPAUSER]	= 0x0164,
	[RFCF]	= 0x0160,
	[TPAUSECR]	= 0x0168,
	[BCFRR]	= 0x016c,
	[MAHR]	= 0x01c0,
	[MALR]	= 0x01c8,
	[TROCR]	= 0x01d0,
	[CDCR]	= 0x01d4,
	[LCCR]	= 0x01d8,
	[CNDCR]	= 0x01dc,
	[CEFCR]	= 0x01e4,
	[FRECR]	= 0x01e8,
	[TSFRCR]	= 0x01ec,
	[TLFRCR]	= 0x01f0,
	[RFCR]	= 0x01f4,
	[MAFCR]	= 0x01f8,
	[RTRATE]	= 0x01fc,

	[EDMR]	= 0x0000,
	[EDTRR]	= 0x0008,
	[EDRRR]	= 0x0010,
	[TDLAR]	= 0x0018,
	[RDLAR]	= 0x0020,
	[EESR]	= 0x0028,
	[EESIPR]	= 0x0030,
	[TRSCER]	= 0x0038,
	[RMFCR]	= 0x0040,
	[TFTR]	= 0x0048,
	[FDR]	= 0x0050,
	[RMCR]	= 0x0058,
	[TFUCR]	= 0x0064,
	[RFOCR]	= 0x0068,
	[RMIIMR] = 0x006C,
	[FCFTR]	= 0x0070,
	[RPADIR]	= 0x0078,
	[TRIMD]	= 0x007c,
	[RBWAR]	= 0x00c8,
	[RDFAR]	= 0x00cc,
	[TBRAR]	= 0x00d4,
	[TDFAR]	= 0x00d8,
};

/* Register Address */
#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR	0xfee00000
#elif defined(CONFIG_CPU_SH7757) || \
	defined(CONFIG_CPU_SH7752) || \
	defined(CONFIG_CPU_SH7753)
#if defined(CONFIG_SH_ETHER_USE_GETHER)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR	0xfee00000
#else
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR	0xfef00000
#endif
#elif defined(CONFIG_CPU_SH7724)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR	0xA4600000
#elif defined(CONFIG_R8A7740)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR	0xE9A00000
#elif defined(CONFIG_RCAR_GEN2)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR	0xEE700200
#elif defined(CONFIG_R7S72100)
#define SH_ETH_TYPE_RZ
#define BASE_IO_ADDR	0xE8203000
#endif

/*
 * Register's bits
 * Copy from Linux driver source code
 */
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
/* EDSR */
enum EDSR_BIT {
	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
};
#define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
#endif

/* EDMR */
enum DMAC_M_BIT {
	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
	EDMR_SRST	= 0x03, /* Receive/Send reset */
	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
	EDMR_EL		= 0x40, /* Litte endian */
#elif defined(SH_ETH_TYPE_ETHER)
	EDMR_SRST	= 0x01,
	EMDR_DESC_R	= 0x30, /* Descriptor reserve size */
	EDMR_EL		= 0x40, /* Litte endian */
#else
	EDMR_SRST = 0x01,
#endif
};

#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
# define EMDR_DESC EDMR_DL1
#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
# define EMDR_DESC EDMR_DL0
#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
# define EMDR_DESC 0
#endif

/* RFLR */
#define RFLR_RFL_MIN	0x05EE	/* Recv Frame length 1518 byte */

/* EDTRR */
enum DMAC_T_BIT {
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
	EDTRR_TRNS = 0x03,
#else
	EDTRR_TRNS = 0x01,
#endif
};

/* GECMR */
enum GECMR_BIT {
#if defined(CONFIG_CPU_SH7757) || \
	defined(CONFIG_CPU_SH7752) || \
	defined(CONFIG_CPU_SH7753)
	GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
#else
	GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
#endif
};

/* EDRRR*/
enum EDRRR_R_BIT {
	EDRRR_R = 0x01,
};

/* TPAUSER */
enum TPAUSER_BIT {
	TPAUSER_TPAUSE = 0x0000ffff,
	TPAUSER_UNLIMITED = 0,
};

/* BCFR */
enum BCFR_BIT {
	BCFR_RPAUSE = 0x0000ffff,
	BCFR_UNLIMITED = 0,
};

/* PIR */
enum PIR_BIT {
	PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
};

/* PSR */
enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };

/* EESR */
enum EESR_BIT {
#if defined(SH_ETH_TYPE_ETHER)
	EESR_TWB  = 0x40000000,
#else
	EESR_TWB  = 0xC0000000,
	EESR_TC1  = 0x20000000,
	EESR_TUC  = 0x10000000,
	EESR_ROC  = 0x80000000,
#endif
	EESR_TABT = 0x04000000,
	EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
#if defined(SH_ETH_TYPE_ETHER)
	EESR_ADE  = 0x00800000,
#endif
	EESR_ECI  = 0x00400000,
	EESR_FTC  = 0x00200000, EESR_TDE  = 0x00100000,
	EESR_TFE  = 0x00080000, EESR_FRC  = 0x00040000,
	EESR_RDE  = 0x00020000, EESR_RFE  = 0x00010000,
#if defined(SH_ETH_TYPE_ETHER)
	EESR_CND  = 0x00000800,
#endif
	EESR_DLC  = 0x00000400,
	EESR_CD   = 0x00000200, EESR_RTO  = 0x00000100,
	EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
	EESR_CELF = 0x00000020, EESR_RRF  = 0x00000010,
	EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
	EESR_PRE  = 0x00000002, EESR_CERF = 0x00000001,
};


#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define TX_CHECK (EESR_TC1 | EESR_FTC)
# define EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
		| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE)

#else
# define TX_CHECK (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO)
# define EESR_ERR_CHECK	(EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
		| EESR_RFRMER | EESR_ADE | EESR_TFE | EESR_TDE | EESR_ECI)
# define TX_ERROR_CEHCK (EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE)
#endif

/* EESIPR */
enum DMAC_IM_BIT {
	DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
	DMAC_M_RABT = 0x02000000,
	DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
	DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
	DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
	DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
	DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
	DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
	DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
	DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
	DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
	DMAC_M_RINT1 = 0x00000001,
};

/* Receive descriptor bit */
enum RD_STS_BIT {
	RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
	RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
	RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
	RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
	RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
	RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
	RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
	RD_RFS1 = 0x00000001,
};
#define RDF1ST	RD_RFP1
#define RDFEND	RD_RFP0
#define RD_RFP	(RD_RFP1|RD_RFP0)

/* RDFFR*/
enum RDFFR_BIT {
	RDFFR_RDLF = 0x01,
};

/* FCFTR */
enum FCFTR_BIT {
	FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
	FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
	FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
};
#define FIFO_F_D_RFF	(FCFTR_RFF2|FCFTR_RFF1|FCFTR_RFF0)
#define FIFO_F_D_RFD	(FCFTR_RFD2|FCFTR_RFD1|FCFTR_RFD0)

/* Transfer descriptor bit */
enum TD_STS_BIT {
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
	defined(SH_ETH_TYPE_RZ)
	TD_TACT = 0x80000000,
#else
	TD_TACT = 0x7fffffff,
#endif
	TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
	TD_TFP0 = 0x10000000,
};
#define TDF1ST	TD_TFP1
#define TDFEND	TD_TFP0
#define TD_TFP	(TD_TFP1|TD_TFP0)

/* RMCR */
enum RECV_RST_BIT { RMCR_RST = 0x01, };
/* ECMR */
enum FELIC_MODE_BIT {
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
	ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
	ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
#endif
	ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
	ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
	ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
	ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
	ECMR_PRM = 0x00000001,
#ifdef CONFIG_CPU_SH7724
	ECMR_RTM = 0x00000010,
#elif defined(CONFIG_RCAR_GEN2)
	ECMR_RTM = 0x00000004,
#endif

};

#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
			ECMR_RXF | ECMR_TXF | ECMR_MCT)
#elif defined(SH_ETH_TYPE_ETHER)
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
#else
#define ECMR_CHG_DM	(ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF | ECMR_MCT)
#endif

/* ECSR */
enum ECSR_STATUS_BIT {
#if defined(SH_ETH_TYPE_ETHER)
	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
#endif
	ECSR_LCHNG = 0x04,
	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
};

#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
#else
# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
			ECSR_LCHNG | ECSR_ICD | ECSIPR_MPDIP)
#endif

/* ECSIPR */
enum ECSIPR_STATUS_MASK_BIT {
#if defined(SH_ETH_TYPE_ETHER)
	ECSIPR_BRCRXIP = 0x20,
	ECSIPR_PSRTOIP = 0x10,
#elif defined(SH_ETY_TYPE_GETHER)
	ECSIPR_PSRTOIP = 0x10,
	ECSIPR_PHYIP = 0x08,
#endif
	ECSIPR_LCHNGIP = 0x04,
	ECSIPR_MPDIP = 0x02,
	ECSIPR_ICDIP = 0x01,
};

#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
#else
# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
				ECSIPR_ICDIP | ECSIPR_MPDIP)
#endif

/* APR */
enum APR_BIT {
	APR_AP = 0x00000004,
};

/* MPR */
enum MPR_BIT {
	MPR_MP = 0x00000006,
};

/* TRSCER */
enum DESC_I_BIT {
	DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
	DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
	DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
	DESC_I_RINT1 = 0x0001,
};

/* RPADIR */
enum RPADIR_BIT {
	RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
	RPADIR_PADR = 0x0003f,
};

#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define RPADIR_INIT (0x00)
#else
# define RPADIR_INIT (RPADIR_PADS1)
#endif

/* FDR */
enum FIFO_SIZE_BIT {
	FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
};

static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
					    int enum_index)
{
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
	const u16 *reg_offset = sh_eth_offset_gigabit;
#elif defined(SH_ETH_TYPE_ETHER)
	const u16 *reg_offset = sh_eth_offset_fast_sh4;
#else
#error
#endif
	return (unsigned long)port->iobase + reg_offset[enum_index];
}

static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
				int enum_index)
{
	outl(data, sh_eth_reg_addr(port, enum_index));
}

static inline unsigned long sh_eth_read(struct sh_eth_info *port,
					int enum_index)
{
	return inl(sh_eth_reg_addr(port, enum_index));
}
Commit	Line	Data
9751ee09	1	/*
1cc0a9f4	2	* sh_eth.h - Driver for Renesas SuperH ethernet controller.
9751ee09	3	*
dcd5a593 NI	4	* Copyright (C) 2008 - 2012 Renesas Solutions Corp.
dcd5a593 NI	5	* Copyright (c) 2008 - 2012 Nobuhiro Iwamatsu
9751ee09 NI	6	* Copyright (c) 2007 Carlos Munoz <[email protected]>
9751ee09 NI	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
9751ee09 NI	9	*/
9751ee09 NI	10
bd3980cc	11	#include <netdev.h>
9751ee09 NI	12	#include <asm/types.h>
	13
	14	#define SHETHER_NAME "sh_eth"
	15
dcd5a593	16	#if defined(CONFIG_SH)
9751ee09 NI	17	/* Malloc returns addresses in the P1 area (cacheable). However we need to
	18	use area P2 (non-cacheable) */
	19	#define ADDR_TO_P2(addr) ((((int)(addr) & ~0xe0000000) \| 0xa0000000))
	20
	21	/* The ethernet controller needs to use physical addresses */
903de461 YS	22	#if defined(CONFIG_SH_32BIT)
	23	#define ADDR_TO_PHY(addr) ((((int)(addr) & ~0xe0000000) \| 0x40000000))
	24	#else
9751ee09	25	#define ADDR_TO_PHY(addr) ((int)(addr) & ~0xe0000000)
903de461	26	#endif
dcd5a593	27	#elif defined(CONFIG_ARM)
5ad565b0 CB	28	#ifndef inl
5ad565b0 CB	29	#define inl readl
dcd5a593	30	#define outl writel
5ad565b0	31	#endif
dcd5a593 NI	32	#define ADDR_TO_PHY(addr) ((int)(addr))
	33	#define ADDR_TO_P2(addr) (addr)
	34	#endif /* defined(CONFIG_SH) */
9751ee09	35
f8b7507d NI	36	/* base padding size is 16 */
	37	#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
	38	#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
	39	#endif
	40
9751ee09 NI	41	/* Number of supported ports */
	42	#define MAX_PORT_NUM 2
	43
	44	/* Buffers must be big enough to hold the largest ethernet frame. Also, rx
	45	buffers must be a multiple of 32 bytes */
	46	#define MAX_BUF_SIZE (48 * 32)
	47
	48	/* The number of tx descriptors must be large enough to point to 5 or more
	49	frames. If each frame uses 2 descriptors, at least 10 descriptors are needed.
	50	We use one descriptor per frame */
	51	#define NUM_TX_DESC 8
	52
	53	/* The size of the tx descriptor is determined by how much padding is used.
	54	4, 20, or 52 bytes of padding can be used */
f8b7507d	55	#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
9751ee09	56
bd3980cc	57	/* Tx descriptor. We always use 3 bytes of padding */
9751ee09 NI	58	struct tx_desc_s {
	59	volatile u32 td0;
	60	u32 td1;
	61	u32 td2; /* Buffer start */
f8b7507d	62	u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
9751ee09 NI	63	};
	64
	65	/* There is no limitation in the number of rx descriptors */
	66	#define NUM_RX_DESC 8
	67
	68	/* The size of the rx descriptor is determined by how much padding is used.
	69	4, 20, or 52 bytes of padding can be used */
f8b7507d	70	#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
f8b7507d NI	71	/* aligned cache line size */
f8b7507d NI	72	#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
9751ee09 NI	73
	74	/* Rx descriptor. We always use 4 bytes of padding */
	75	struct rx_desc_s {
	76	volatile u32 rd0;
	77	volatile u32 rd1;
	78	u32 rd2; /* Buffer start */
f8b7507d	79	u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
9751ee09 NI	80	};
9751ee09 NI	81
bd3980cc	82	struct sh_eth_info {
000889cd	83	struct tx_desc_s *tx_desc_alloc;
9751ee09 NI	84	struct tx_desc_s *tx_desc_base;
9751ee09 NI	85	struct tx_desc_s *tx_desc_cur;
000889cd	86	struct rx_desc_s *rx_desc_alloc;
9751ee09 NI	87	struct rx_desc_s *rx_desc_base;
9751ee09 NI	88	struct rx_desc_s *rx_desc_cur;
000889cd	89	u8 *rx_buf_alloc;
9751ee09 NI	90	u8 *rx_buf_base;
	91	u8 mac_addr[6];
	92	u8 phy_addr;
bd3980cc	93	struct eth_device *dev;
bd1024b0	94	struct phy_device *phydev;
fbfb5115	95	void __iomem *iobase;
9751ee09 NI	96	};
9751ee09 NI	97
bd3980cc	98	struct sh_eth_dev {
9751ee09	99	int port;
bd3980cc	100	struct sh_eth_info port_info[MAX_PORT_NUM];
9751ee09 NI	101	};
9751ee09 NI	102
49afb8ca YS	103	/* from linux/drivers/net/ethernet/renesas/sh_eth.h */
	104	enum {
	105	/* E-DMAC registers */
	106	EDSR = 0,
	107	EDMR,
	108	EDTRR,
	109	EDRRR,
	110	EESR,
	111	EESIPR,
	112	TDLAR,
	113	TDFAR,
	114	TDFXR,
	115	TDFFR,
	116	RDLAR,
	117	RDFAR,
	118	RDFXR,
	119	RDFFR,
	120	TRSCER,
	121	RMFCR,
	122	TFTR,
	123	FDR,
	124	RMCR,
	125	EDOCR,
	126	TFUCR,
	127	RFOCR,
	128	FCFTR,
	129	RPADIR,
	130	TRIMD,
	131	RBWAR,
	132	TBRAR,
	133
	134	/* Ether registers */
	135	ECMR,
	136	ECSR,
	137	ECSIPR,
	138	PIR,
	139	PSR,
	140	RDMLR,
	141	PIPR,
	142	RFLR,
	143	IPGR,
	144	APR,
	145	MPR,
	146	PFTCR,
	147	PFRCR,
	148	RFCR,
	149	RFCF,
	150	TPAUSER,
	151	TPAUSECR,
	152	BCFR,
	153	BCFRR,
	154	GECMR,
	155	BCULR,
	156	MAHR,
	157	MALR,
	158	TROCR,
	159	CDCR,
	160	LCCR,
	161	CNDCR,
	162	CEFCR,
	163	FRECR,
	164	TSFRCR,
	165	TLFRCR,
	166	CERCR,
167	CEECR,
8707678c	168	RMIIMR, /* R8A7790 */
49afb8ca YS	169	MAFCR,
	170	RTRATE,
	171	CSMR,
	172	RMII_MII,
	173
	174	/* This value must be written at last. */
	175	SH_ETH_MAX_REGISTER_OFFSET,
	176	};
	177
	178	static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
	179	[EDSR] = 0x0000,
	180	[EDMR] = 0x0400,
	181	[EDTRR] = 0x0408,
	182	[EDRRR] = 0x0410,
	183	[EESR] = 0x0428,
	184	[EESIPR] = 0x0430,
	185	[TDLAR] = 0x0010,
	186	[TDFAR] = 0x0014,
	187	[TDFXR] = 0x0018,
	188	[TDFFR] = 0x001c,
	189	[RDLAR] = 0x0030,
	190	[RDFAR] = 0x0034,
	191	[RDFXR] = 0x0038,
	192	[RDFFR] = 0x003c,
	193	[TRSCER] = 0x0438,
	194	[RMFCR] = 0x0440,
	195	[TFTR] = 0x0448,
	196	[FDR] = 0x0450,
	197	[RMCR] = 0x0458,
	198	[RPADIR] = 0x0460,
	199	[FCFTR] = 0x0468,
	200	[CSMR] = 0x04E4,
	201
	202	[ECMR] = 0x0500,
	203	[ECSR] = 0x0510,
	204	[ECSIPR] = 0x0518,
	205	[PIR] = 0x0520,
	206	[PSR] = 0x0528,
	207	[PIPR] = 0x052c,
	208	[RFLR] = 0x0508,
	209	[APR] = 0x0554,
	210	[MPR] = 0x0558,
	211	[PFTCR] = 0x055c,
	212	[PFRCR] = 0x0560,
	213	[TPAUSER] = 0x0564,
	214	[GECMR] = 0x05b0,
	215	[BCULR] = 0x05b4,
	216	[MAHR] = 0x05c0,
	217	[MALR] = 0x05c8,
	218	[TROCR] = 0x0700,
	219	[CDCR] = 0x0708,
	220	[LCCR] = 0x0710,
	221	[CEFCR] = 0x0740,
	222	[FRECR] = 0x0748,
	223	[TSFRCR] = 0x0750,
	224	[TLFRCR] = 0x0758,
	225	[RFCR] = 0x0760,
	226	[CERCR] = 0x0768,
	227	[CEECR] = 0x0770,
	228	[MAFCR] = 0x0778,
	229	[RMII_MII] = 0x0790,
	230	};
	231
	232	static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
233	[ECMR] = 0x0100,
234	[RFLR] = 0x0108,
235	[ECSR] = 0x0110,
236	[ECSIPR] = 0x0118,
237	[PIR] = 0x0120,
238	[PSR] = 0x0128,
239	[RDMLR] = 0x0140,
240	[IPGR] = 0x0150,
241	[APR] = 0x0154,
242	[MPR] = 0x0158,
243	[TPAUSER] = 0x0164,
244	[RFCF] = 0x0160,
245	[TPAUSECR] = 0x0168,
246	[BCFRR] = 0x016c,
247	[MAHR] = 0x01c0,
248	[MALR] = 0x01c8,
249	[TROCR] = 0x01d0,
250	[CDCR] = 0x01d4,
251	[LCCR] = 0x01d8,
252	[CNDCR] = 0x01dc,
253	[CEFCR] = 0x01e4,
254	[FRECR] = 0x01e8,
255	[TSFRCR] = 0x01ec,
256	[TLFRCR] = 0x01f0,
257	[RFCR] = 0x01f4,
258	[MAFCR] = 0x01f8,
259	[RTRATE] = 0x01fc,
260
261	[EDMR] = 0x0000,
262	[EDTRR] = 0x0008,
263	[EDRRR] = 0x0010,
264	[TDLAR] = 0x0018,
265	[RDLAR] = 0x0020,
266	[EESR] = 0x0028,
267	[EESIPR] = 0x0030,
268	[TRSCER] = 0x0038,
269	[RMFCR] = 0x0040,
270	[TFTR] = 0x0048,
271	[FDR] = 0x0050,
272	[RMCR] = 0x0058,
273	[TFUCR] = 0x0064,
274	[RFOCR] = 0x0068,
8707678c	275	[RMIIMR] = 0x006C,
49afb8ca YS	276	[FCFTR] = 0x0070,
	277	[RPADIR] = 0x0078,
	278	[TRIMD] = 0x007c,
	279	[RBWAR] = 0x00c8,
	280	[RDFAR] = 0x00cc,
	281	[TBRAR] = 0x00d4,
	282	[TDFAR] = 0x00d8,
	283	};
	284
9751ee09	285	/* Register Address */
49afb8ca	286	#if defined(CONFIG_CPU_SH7763) \|\| defined(CONFIG_CPU_SH7734)
26235093	287	#define SH_ETH_TYPE_GETHER
9751ee09	288	#define BASE_IO_ADDR 0xfee00000
3067f81f YS	289	#elif defined(CONFIG_CPU_SH7757) \|\| \
	290	defined(CONFIG_CPU_SH7752) \|\| \
	291	defined(CONFIG_CPU_SH7753)
631fea8f YS	292	#if defined(CONFIG_SH_ETHER_USE_GETHER)
	293	#define SH_ETH_TYPE_GETHER
	294	#define BASE_IO_ADDR 0xfee00000
	295	#else
26235093	296	#define SH_ETH_TYPE_ETHER
903de461	297	#define BASE_IO_ADDR 0xfef00000
631fea8f	298	#endif
3bb4cc31	299	#elif defined(CONFIG_CPU_SH7724)
26235093	300	#define SH_ETH_TYPE_ETHER
3bb4cc31	301	#define BASE_IO_ADDR 0xA4600000
dcd5a593 NI	302	#elif defined(CONFIG_R8A7740)
	303	#define SH_ETH_TYPE_GETHER
	304	#define BASE_IO_ADDR 0xE9A00000
effb7902	305	#elif defined(CONFIG_RCAR_GEN2)
8707678c NI	306	#define SH_ETH_TYPE_ETHER
8707678c NI	307	#define BASE_IO_ADDR 0xEE700200
62cbddc4 NI	308	#elif defined(CONFIG_R7S72100)
	309	#define SH_ETH_TYPE_RZ
	310	#define BASE_IO_ADDR 0xE8203000
903de461 YS	311	#endif
903de461 YS	312
9751ee09 NI	313	/*
	314	* Register's bits
	315	* Copy from Linux driver source code
	316	*/
62cbddc4	317	#if defined(SH_ETH_TYPE_GETHER) \|\| defined(SH_ETH_TYPE_RZ)
9751ee09 NI	318	/* EDSR */
	319	enum EDSR_BIT {
	320	EDSR_ENT = 0x01, EDSR_ENR = 0x02,
	321	};
	322	#define EDSR_ENALL (EDSR_ENT\|EDSR_ENR)
	323	#endif
	324
	325	/* EDMR */
	326	enum DMAC_M_BIT {
	327	EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
62cbddc4	328	#if defined(SH_ETH_TYPE_GETHER) \|\| defined(SH_ETH_TYPE_RZ)
ee6ec5d4	329	EDMR_SRST = 0x03, /* Receive/Send reset */
9751ee09 NI	330	EMDR_DESC_R = 0x30, /* Descriptor reserve size */
9751ee09 NI	331	EDMR_EL = 0x40, /* Litte endian */
26235093	332	#elif defined(SH_ETH_TYPE_ETHER)
903de461 YS	333	EDMR_SRST = 0x01,
	334	EMDR_DESC_R = 0x30, /* Descriptor reserve size */
	335	EDMR_EL = 0x40, /* Litte endian */
26235093	336	#else
9751ee09 NI	337	EDMR_SRST = 0x01,
	338	#endif
	339	};
	340
f8b7507d NI	341	#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
	342	# define EMDR_DESC EDMR_DL1
	343	#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
	344	# define EMDR_DESC EDMR_DL0
	345	#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
	346	# define EMDR_DESC 0
	347	#endif
	348
9751ee09 NI	349	/* RFLR */
	350	#define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
	351
	352	/* EDTRR */
	353	enum DMAC_T_BIT {
62cbddc4	354	#if defined(SH_ETH_TYPE_GETHER) \|\| defined(SH_ETH_TYPE_RZ)
9751ee09 NI	355	EDTRR_TRNS = 0x03,
	356	#else
	357	EDTRR_TRNS = 0x01,
	358	#endif
	359	};
	360
	361	/* GECMR */
	362	enum GECMR_BIT {
3067f81f YS	363	#if defined(CONFIG_CPU_SH7757) \|\| \
	364	defined(CONFIG_CPU_SH7752) \|\| \
	365	defined(CONFIG_CPU_SH7753)
631fea8f YS	366	GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
631fea8f YS	367	#else
09fcc8b5	368	GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
631fea8f	369	#endif
9751ee09 NI	370	};
	371
	372	/* EDRRR*/
	373	enum EDRRR_R_BIT {
	374	EDRRR_R = 0x01,
	375	};
	376
	377	/* TPAUSER */
	378	enum TPAUSER_BIT {
	379	TPAUSER_TPAUSE = 0x0000ffff,
	380	TPAUSER_UNLIMITED = 0,
	381	};
	382
	383	/* BCFR */
	384	enum BCFR_BIT {
	385	BCFR_RPAUSE = 0x0000ffff,
	386	BCFR_UNLIMITED = 0,
	387	};
	388
	389	/* PIR */
	390	enum PIR_BIT {
	391	PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
	392	};
	393
	394	/* PSR */
	395	enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
	396
	397	/* EESR */
	398	enum EESR_BIT {
26235093	399	#if defined(SH_ETH_TYPE_ETHER)
9751ee09 NI	400	EESR_TWB = 0x40000000,
	401	#else
	402	EESR_TWB = 0xC0000000,
	403	EESR_TC1 = 0x20000000,
	404	EESR_TUC = 0x10000000,
	405	EESR_ROC = 0x80000000,
	406	#endif
	407	EESR_TABT = 0x04000000,
	408	EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
26235093	409	#if defined(SH_ETH_TYPE_ETHER)
9751ee09 NI	410	EESR_ADE = 0x00800000,
	411	#endif
	412	EESR_ECI = 0x00400000,
	413	EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
	414	EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
	415	EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
26235093	416	#if defined(SH_ETH_TYPE_ETHER)
9751ee09 NI	417	EESR_CND = 0x00000800,
	418	#endif
	419	EESR_DLC = 0x00000400,
	420	EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
	421	EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
	422	EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
1dbd7280	423	EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
9751ee09 NI	424	EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
	425	};
	426
	427
62cbddc4	428	#if defined(SH_ETH_TYPE_GETHER) \|\| defined(SH_ETH_TYPE_RZ)
9751ee09 NI	429	# define TX_CHECK (EESR_TC1 \| EESR_FTC)
	430	# define EESR_ERR_CHECK (EESR_TWB \| EESR_TABT \| EESR_RABT \| EESR_RDE \
	431	\| EESR_RFRMER \| EESR_TFE \| EESR_TDE \| EESR_ECI)
	432	# define TX_ERROR_CEHCK (EESR_TWB \| EESR_TABT \| EESR_TDE \| EESR_TFE)
	433
	434	#else
	435	# define TX_CHECK (EESR_FTC \| EESR_CND \| EESR_DLC \| EESR_CD \| EESR_RTO)
	436	# define EESR_ERR_CHECK (EESR_TWB \| EESR_TABT \| EESR_RABT \| EESR_RDE \
	437	\| EESR_RFRMER \| EESR_ADE \| EESR_TFE \| EESR_TDE \| EESR_ECI)
	438	# define TX_ERROR_CEHCK (EESR_TWB \| EESR_TABT \| EESR_ADE \| EESR_TDE \| EESR_TFE)
	439	#endif
	440
	441	/* EESIPR */
	442	enum DMAC_IM_BIT {
	443	DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
	444	DMAC_M_RABT = 0x02000000,
	445	DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
	446	DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
	447	DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
	448	DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
	449	DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
	450	DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
	451	DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
	452	DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
	453	DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
	454	DMAC_M_RINT1 = 0x00000001,
	455	};
	456
	457	/* Receive descriptor bit */
	458	enum RD_STS_BIT {
	459	RD_RACT = 0x80000000, RD_RDLE = 0x40000000,
	460	RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
	461	RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
	462	RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
	463	RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
	464	RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
	465	RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
	466	RD_RFS1 = 0x00000001,
	467	};
	468	#define RDF1ST RD_RFP1
	469	#define RDFEND RD_RFP0
	470	#define RD_RFP (RD_RFP1\|RD_RFP0)
	471
	472	/* RDFFR*/
	473	enum RDFFR_BIT {
	474	RDFFR_RDLF = 0x01,
	475	};
	476
	477	/* FCFTR */
	478	enum FCFTR_BIT {
	479	FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
	480	FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
	481	FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
	482	};
	483	#define FIFO_F_D_RFF (FCFTR_RFF2\|FCFTR_RFF1\|FCFTR_RFF0)
	484	#define FIFO_F_D_RFD (FCFTR_RFD2\|FCFTR_RFD1\|FCFTR_RFD0)
	485
	486	/* Transfer descriptor bit */
	487	enum TD_STS_BIT {
62cbddc4 NI	488	#if defined(SH_ETH_TYPE_GETHER) \|\| defined(SH_ETH_TYPE_ETHER) \|\| \
62cbddc4 NI	489	defined(SH_ETH_TYPE_RZ)
9751ee09 NI	490	TD_TACT = 0x80000000,
	491	#else
	492	TD_TACT = 0x7fffffff,
	493	#endif
	494	TD_TDLE = 0x40000000, TD_TFP1 = 0x20000000,
	495	TD_TFP0 = 0x10000000,
	496	};
	497	#define TDF1ST TD_TFP1
	498	#define TDFEND TD_TFP0
	499	#define TD_TFP (TD_TFP1\|TD_TFP0)
	500
	501	/* RMCR */
	502	enum RECV_RST_BIT { RMCR_RST = 0x01, };
	503	/* ECMR */
	504	enum FELIC_MODE_BIT {
62cbddc4	505	#if defined(SH_ETH_TYPE_GETHER) \|\| defined(SH_ETH_TYPE_RZ)
e2752db0 NI	506	ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
e2752db0 NI	507	ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
9751ee09 NI	508	#endif
	509	ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
	510	ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
	511	ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
	512	ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004, ECMR_DM = 0x00000002,
	513	ECMR_PRM = 0x00000001,
3bb4cc31 NI	514	#ifdef CONFIG_CPU_SH7724
3bb4cc31 NI	515	ECMR_RTM = 0x00000010,
effb7902	516	#elif defined(CONFIG_RCAR_GEN2)
8707678c	517	ECMR_RTM = 0x00000004,
3bb4cc31 NI	518	#endif
3bb4cc31 NI	519
9751ee09 NI	520	};
9751ee09 NI	521
62cbddc4	522	#if defined(SH_ETH_TYPE_GETHER) \|\| defined(SH_ETH_TYPE_RZ)
e2752db0 NI	523	#define ECMR_CHG_DM (ECMR_TRCCM \| ECMR_RZPF \| ECMR_ZPF \| ECMR_PFR \| \
e2752db0 NI	524	ECMR_RXF \| ECMR_TXF \| ECMR_MCT)
26235093	525	#elif defined(SH_ETH_TYPE_ETHER)
3bb4cc31	526	#define ECMR_CHG_DM (ECMR_ZPF \| ECMR_PFR \| ECMR_RXF \| ECMR_TXF)
9751ee09	527	#else
903de461	528	#define ECMR_CHG_DM (ECMR_ZPF \| ECMR_PFR \| ECMR_RXF \| ECMR_TXF \| ECMR_MCT)
9751ee09 NI	529	#endif
	530
	531	/* ECSR */
	532	enum ECSR_STATUS_BIT {
26235093	533	#if defined(SH_ETH_TYPE_ETHER)
9751ee09 NI	534	ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
	535	#endif
	536	ECSR_LCHNG = 0x04,
	537	ECSR_MPD = 0x02, ECSR_ICD = 0x01,
	538	};
	539
62cbddc4	540	#if defined(SH_ETH_TYPE_GETHER) \|\| defined(SH_ETH_TYPE_RZ)
9751ee09 NI	541	# define ECSR_INIT (ECSR_ICD \| ECSIPR_MPDIP)
	542	#else
	543	# define ECSR_INIT (ECSR_BRCRX \| ECSR_PSRTO \| \
	544	ECSR_LCHNG \| ECSR_ICD \| ECSIPR_MPDIP)
	545	#endif
	546
	547	/* ECSIPR */
	548	enum ECSIPR_STATUS_MASK_BIT {
26235093	549	#if defined(SH_ETH_TYPE_ETHER)
a6616efb	550	ECSIPR_BRCRXIP = 0x20,
ee6ec5d4	551	ECSIPR_PSRTOIP = 0x10,
26235093	552	#elif defined(SH_ETY_TYPE_GETHER)
ee6ec5d4 NI	553	ECSIPR_PSRTOIP = 0x10,
ee6ec5d4 NI	554	ECSIPR_PHYIP = 0x08,
a6616efb	555	#endif
9751ee09	556	ECSIPR_LCHNGIP = 0x04,
ee6ec5d4 NI	557	ECSIPR_MPDIP = 0x02,
ee6ec5d4 NI	558	ECSIPR_ICDIP = 0x01,
9751ee09 NI	559	};
9751ee09 NI	560
62cbddc4	561	#if defined(SH_ETH_TYPE_GETHER) \|\| defined(SH_ETH_TYPE_RZ)
9751ee09 NI	562	# define ECSIPR_INIT (ECSIPR_LCHNGIP \| ECSIPR_ICDIP \| ECSIPR_MPDIP)
	563	#else
	564	# define ECSIPR_INIT (ECSIPR_BRCRXIP \| ECSIPR_PSRTOIP \| ECSIPR_LCHNGIP \| \
	565	ECSIPR_ICDIP \| ECSIPR_MPDIP)
	566	#endif
	567
	568	/* APR */
	569	enum APR_BIT {
	570	APR_AP = 0x00000004,
	571	};
	572
	573	/* MPR */
	574	enum MPR_BIT {
	575	MPR_MP = 0x00000006,
	576	};
	577
	578	/* TRSCER */
	579	enum DESC_I_BIT {
	580	DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
	581	DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
	582	DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
	583	DESC_I_RINT1 = 0x0001,
	584	};
	585
	586	/* RPADIR */
	587	enum RPADIR_BIT {
	588	RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
	589	RPADIR_PADR = 0x0003f,
	590	};
	591
62cbddc4	592	#if defined(SH_ETH_TYPE_GETHER) \|\| defined(SH_ETH_TYPE_RZ)
9751ee09 NI	593	# define RPADIR_INIT (0x00)
	594	#else
	595	# define RPADIR_INIT (RPADIR_PADS1)
	596	#endif
	597
	598	/* FDR */
	599	enum FIFO_SIZE_BIT {
	600	FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007,
	601	};
49afb8ca	602
fbfb5115	603	static inline unsigned long sh_eth_reg_addr(struct sh_eth_info *port,
49afb8ca YS	604	int enum_index)
49afb8ca YS	605	{
f6ac626c	606	#if defined(SH_ETH_TYPE_GETHER) \|\| defined(SH_ETH_TYPE_RZ)
49afb8ca YS	607	const u16 *reg_offset = sh_eth_offset_gigabit;
	608	#elif defined(SH_ETH_TYPE_ETHER)
	609	const u16 *reg_offset = sh_eth_offset_fast_sh4;
	610	#else
	611	#error
	612	#endif
fbfb5115	613	return (unsigned long)port->iobase + reg_offset[enum_index];
49afb8ca YS	614	}
49afb8ca YS	615
fbfb5115	616	static inline void sh_eth_write(struct sh_eth_info *port, unsigned long data,
49afb8ca YS	617	int enum_index)
49afb8ca YS	618	{
fbfb5115	619	outl(data, sh_eth_reg_addr(port, enum_index));
49afb8ca YS	620	}
49afb8ca YS	621
fbfb5115	622	static inline unsigned long sh_eth_read(struct sh_eth_info *port,
49afb8ca YS	623	int enum_index)
49afb8ca YS	624	{
fbfb5115	625	return inl(sh_eth_reg_addr(port, enum_index));
49afb8ca	626	}