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drivers: ram: rockchip: Fix dram channels calculation for rk3399
[J-u-boot.git] / drivers / ram / mpc83xx_sdram.c
CommitLineData
e4061556
MS		 1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2018
4 * Mario Six, Guntermann & Drunck GmbH, [email protected]
5 */
6
7#include <common.h>
8#include <dm.h>
9b4a205f 9#include <init.h>
f7ae49fc 10#include <log.h>
e4061556 11#include <ram.h>
cd93d625 12#include <asm/bitops.h>
401d1c4f 13#include <asm/global_data.h>
e4061556
MS		 14#include <dt-bindings/memory/mpc83xx-sdram.h>
15
16DECLARE_GLOBAL_DATA_PTR;
17
18/* Masks for the CS config register */
19static const u32 CSCONFIG_ENABLE = 0x80000000;
20
21static const u32 BANK_BITS_2;
22static const u32 BANK_BITS_3 = 0x00004000;
23
24static const u32 ROW_BITS_12;
25static const u32 ROW_BITS_13 = 0x00000100;
26static const u32 ROW_BITS_14 = 0x00000200;
27
28static const u32 COL_BITS_8;
29static const u32 COL_BITS_9 = 0x00000001;
30static const u32 COL_BITS_10 = 0x00000002;
31static const u32 COL_BITS_11 = 0x00000003;
32
33/* Shifts for the DDR SDRAM Timing Configuration 3 register */
34static const uint TIMING_CFG3_EXT_REFREC_SHIFT = (31 - 15);
35
36/* Shifts for the DDR SDRAM Timing Configuration 0 register */
37static const uint TIMING_CFG0_RWT_SHIFT = (31 - 1);
38static const uint TIMING_CFG0_WRT_SHIFT = (31 - 3);
39static const uint TIMING_CFG0_RRT_SHIFT = (31 - 5);
40static const uint TIMING_CFG0_WWT_SHIFT = (31 - 7);
41static const uint TIMING_CFG0_ACT_PD_EXIT_SHIFT = (31 - 11);
42static const uint TIMING_CFG0_PRE_PD_EXIT_SHIFT = (31 - 15);
43static const uint TIMING_CFG0_ODT_PD_EXIT_SHIFT = (31 - 23);
44static const uint TIMING_CFG0_MRS_CYC_SHIFT = (31 - 31);
45
46/* Shifts for the DDR SDRAM Timing Configuration 1 register */
47static const uint TIMING_CFG1_PRETOACT_SHIFT = (31 - 3);
48static const uint TIMING_CFG1_ACTTOPRE_SHIFT = (31 - 7);
49static const uint TIMING_CFG1_ACTTORW_SHIFT = (31 - 11);
50static const uint TIMING_CFG1_CASLAT_SHIFT = (31 - 15);
51static const uint TIMING_CFG1_REFREC_SHIFT = (31 - 19);
52static const uint TIMING_CFG1_WRREC_SHIFT = (31 - 23);
53static const uint TIMING_CFG1_ACTTOACT_SHIFT = (31 - 27);
54static const uint TIMING_CFG1_WRTORD_SHIFT = (31 - 31);
55
56/* Shifts for the DDR SDRAM Timing Configuration 2 register */
57static const uint TIMING_CFG2_CPO_SHIFT = (31 - 8);
58static const uint TIMING_CFG2_WR_DATA_DELAY_SHIFT = (31 - 21);
59static const uint TIMING_CFG2_ADD_LAT_SHIFT = (31 - 3);
60static const uint TIMING_CFG2_WR_LAT_DELAY_SHIFT = (31 - 12);
61static const uint TIMING_CFG2_RD_TO_PRE_SHIFT = (31 - 18);
62static const uint TIMING_CFG2_CKE_PLS_SHIFT = (31 - 25);
63static const uint TIMING_CFG2_FOUR_ACT_SHIFT;
64
65/* Shifts for the DDR SDRAM Control Configuration register */
66static const uint SDRAM_CFG_SREN_SHIFT = (31 - 1);
67static const uint SDRAM_CFG_ECC_EN_SHIFT = (31 - 2);
68static const uint SDRAM_CFG_RD_EN_SHIFT = (31 - 3);
69static const uint SDRAM_CFG_SDRAM_TYPE_SHIFT = (31 - 7);
70static const uint SDRAM_CFG_DYN_PWR_SHIFT = (31 - 10);
71static const uint SDRAM_CFG_DBW_SHIFT = (31 - 12);
72static const uint SDRAM_CFG_NCAP_SHIFT = (31 - 14);
73static const uint SDRAM_CFG_2T_EN_SHIFT = (31 - 16);
74static const uint SDRAM_CFG_BA_INTLV_CTL_SHIFT = (31 - 23);
75static const uint SDRAM_CFG_PCHB8_SHIFT = (31 - 27);
76static const uint SDRAM_CFG_HSE_SHIFT = (31 - 28);
77static const uint SDRAM_CFG_BI_SHIFT = (31 - 31);
78
79/* Shifts for the DDR SDRAM Control Configuration 2 register */
80static const uint SDRAM_CFG2_FRC_SR_SHIFT = (31 - 0);
81static const uint SDRAM_CFG2_DLL_RST_DIS = (31 - 2);
82static const uint SDRAM_CFG2_DQS_CFG = (31 - 5);
83static const uint SDRAM_CFG2_ODT_CFG = (31 - 10);
84static const uint SDRAM_CFG2_NUM_PR = (31 - 19);
85
86/* Shifts for the DDR SDRAM Mode register */
87static const uint SDRAM_MODE_ESD_SHIFT = (31 - 15);
88static const uint SDRAM_MODE_SD_SHIFT = (31 - 31);
89
90/* Shifts for the DDR SDRAM Mode 2 register */
91static const uint SDRAM_MODE2_ESD2_SHIFT = (31 - 15);
92static const uint SDRAM_MODE2_ESD3_SHIFT = (31 - 31);
93
94/* Shifts for the DDR SDRAM Interval Configuration register */
95static const uint SDRAM_INTERVAL_REFINT_SHIFT = (31 - 15);
96static const uint SDRAM_INTERVAL_BSTOPRE_SHIFT = (31 - 31);
97
98/* Mask for the DDR SDRAM Mode Control register */
99static const u32 SDRAM_CFG_MEM_EN = 0x80000000;
100
101int dram_init(void)
102{
103 struct udevice *ram_ctrl;
104 int ret;
105
106 /* Current assumption: There is only one RAM controller */
107 ret = uclass_first_device_err(UCLASS_RAM, &ram_ctrl);
108 if (ret) {
109 debug("%s: uclass_first_device_err failed: %d\n",
110 __func__, ret);
111 return ret;
112 }
113
114 /* FIXME([email protected]): Set gd->ram_size? */
115
116 return 0;
117}
118
119phys_size_t get_effective_memsize(void)
120{
121 if (!IS_ENABLED(CONFIG_VERY_BIG_RAM))
122 return gd->ram_size;
123
124 /* Limit stack to what we can reasonable map */
125 return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
126 CONFIG_MAX_MEM_MAPPED : gd->ram_size);
127}
128
129/**
130 * struct mpc83xx_sdram_priv - Private data for MPC83xx RAM controllers
131 * @total_size: The total size of all RAM modules associated with this RAM
132 * controller in bytes
133 */
134struct mpc83xx_sdram_priv {
135 ulong total_size;
136};
137
138/**
139 * mpc83xx_sdram_static_init() - Statically initialize a RAM module.
140 * @node: Device tree node associated with ths module in question
141 * @cs: The chip select to use for this RAM module
142 * @mapaddr: The address where the RAM module should be mapped
143 * @size: The size of the RAM module to be mapped in bytes
144 *
145 * Return: 0 if OK, -ve on error
146 */
147static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
148{
149 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
150 u32 msize = size;
151 u32 msize_log2 = __ilog2(msize);
152 u32 auto_precharge, odt_rd_cfg, odt_wr_cfg, bank_bits, row_bits,
153 col_bits;
154 u32 bank_bits_mask, row_bits_mask, col_bits_mask;
155
156 /* Configure the DDR local access window */
157 out_be32(&im->sysconf.ddrlaw[cs].bar, mapaddr & 0xfffff000);
158 out_be32(&im->sysconf.ddrlaw[cs].ar, LBLAWAR_EN | (msize_log2 - 1));
159
160 out_be32(&im->ddr.csbnds[cs].csbnds, (msize - 1) >> 24);
161
162 auto_precharge = ofnode_read_u32_default(node, "auto_precharge", 0);
163 switch (auto_precharge) {
164 case AUTO_PRECHARGE_ENABLE:
165 case AUTO_PRECHARGE_DISABLE:
166 break;
167 default:
168 debug("%s: auto_precharge value %d invalid.\n",
169 ofnode_get_name(node), auto_precharge);
170 return -EINVAL;
171 }
172
173 odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0);
174 switch (odt_rd_cfg) {
175 case ODT_RD_ONLY_OTHER_DIMM:
61abced7 176 if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
8439e99d 177 !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
e4061556
MS		 178 debug("%s: odt_rd_cfg value %d invalid.\n",
179 ofnode_get_name(node), odt_rd_cfg);
180 return -EINVAL;
181 }
182 /* fall through */
183 case ODT_RD_NEVER:
184 case ODT_RD_ONLY_CURRENT:
185 case ODT_RD_ONLY_OTHER_CS:
4bc97a3b 186 if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
9403fc41 187 !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
61abced7 188 !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
8439e99d 189 !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
e4061556
MS		 190 debug("%s: odt_rd_cfg value %d invalid.\n",
191 ofnode_get_name(node), odt_rd_cfg);
192 return -EINVAL;
193 }
194 /* fall through */
195 /* Only MPC832x knows this value */
196 case ODT_RD_ALL:
197 break;
198 default:
199 debug("%s: odt_rd_cfg value %d invalid.\n",
200 ofnode_get_name(node), odt_rd_cfg);
201 return -EINVAL;
202 }
203
204 odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0);
205 switch (odt_wr_cfg) {
206 case ODT_WR_ONLY_OTHER_DIMM:
61abced7 207 if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
8439e99d 208 !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
e4061556
MS		 209 debug("%s: odt_wr_cfg value %d invalid.\n",
210 ofnode_get_name(node), odt_wr_cfg);
211 return -EINVAL;
212 }
213 /* fall through */
214 case ODT_WR_NEVER:
215 case ODT_WR_ONLY_CURRENT:
216 case ODT_WR_ONLY_OTHER_CS:
4bc97a3b 217 if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
9403fc41 218 !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
61abced7 219 !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
8439e99d 220 !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
e4061556
MS		 221 debug("%s: odt_wr_cfg value %d invalid.\n",
222 ofnode_get_name(node), odt_wr_cfg);
223 return -EINVAL;
224 }
225 /* fall through */
226 /* MPC832x only knows this value */
227 case ODT_WR_ALL:
228 break;
229 default:
230 debug("%s: odt_wr_cfg value %d invalid.\n",
231 ofnode_get_name(node), odt_wr_cfg);
232 return -EINVAL;
233 }
234
235 bank_bits = ofnode_read_u32_default(node, "bank_bits", 0);
236 switch (bank_bits) {
237 case 2:
238 bank_bits_mask = BANK_BITS_2;
239 break;
240 case 3:
241 bank_bits_mask = BANK_BITS_3;
242 break;
243 default:
244 debug("%s: bank_bits value %d invalid.\n",
245 ofnode_get_name(node), bank_bits);
246 return -EINVAL;
247 }
248
249 row_bits = ofnode_read_u32_default(node, "row_bits", 0);
250 switch (row_bits) {
251 case 12:
252 row_bits_mask = ROW_BITS_12;
253 break;
254 case 13:
255 row_bits_mask = ROW_BITS_13;
256 break;
257 case 14:
258 row_bits_mask = ROW_BITS_14;
259 break;
260 default:
261 debug("%s: row_bits value %d invalid.\n",
262 ofnode_get_name(node), row_bits);
263 return -EINVAL;
264 }
265
266 col_bits = ofnode_read_u32_default(node, "col_bits", 0);
267 switch (col_bits) {
268 case 8:
269 col_bits_mask = COL_BITS_8;
270 break;
271 case 9:
272 col_bits_mask = COL_BITS_9;
273 break;
274 case 10:
275 col_bits_mask = COL_BITS_10;
276 break;
277 case 11:
278 col_bits_mask = COL_BITS_11;
279 break;
280 default:
281 debug("%s: col_bits value %d invalid.\n",
282 ofnode_get_name(node), col_bits);
283 return -EINVAL;
284 }
285
286 /* Write CS config value */
287 out_be32(&im->ddr.cs_config[cs], CSCONFIG_ENABLE | auto_precharge |
288 odt_rd_cfg | odt_wr_cfg |
289 bank_bits_mask | row_bits_mask |
290 col_bits_mask);
291 return 0;
292}
293
294/**
295 * mpc83xx_sdram_spd_init() - Initialize a RAM module using a SPD flash.
296 * @node: Device tree node associated with ths module in question
297 * @cs: The chip select to use for this RAM module
298 * @mapaddr: The address where the RAM module should be mapped
299 * @size: The size of the RAM module to be mapped in bytes
300 *
301 * Return: 0 if OK, -ve on error
302 */
303static int mpc83xx_sdram_spd_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
304{
305 /* TODO([email protected]): Implement */
306 return 0;
307}
308
d1998a9f 309static int mpc83xx_sdram_of_to_plat(struct udevice *dev)
e4061556
MS		 310{
311 return 0;
312}
313
314static int mpc83xx_sdram_probe(struct udevice *dev)
315{
316 struct mpc83xx_sdram_priv *priv = dev_get_priv(dev);
317 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
318 int ret = 0;
319 ofnode subnode;
320 /* DDR control driver register values */
321 u32 dso, pz_override, nz_override, odt_term, ddr_type, mvref_sel, m_odr;
322 u32 ddrcdr;
323 /* DDR SDRAM Clock Control register values */
324 u32 clock_adjust;
325 /* DDR SDRAM Timing Configuration 3 register values */
326 u32 ext_refresh_rec, ext_refresh_rec_mask;
327 /* DDR SDRAM Timing Configuration 0 register values */
328 u32 read_to_write, write_to_read, read_to_read, write_to_write,
329 active_powerdown_exit, precharge_powerdown_exit,
330 odt_powerdown_exit, mode_reg_set_cycle;
331 u32 timing_cfg_0;
332 /* DDR SDRAM Timing Configuration 1 register values */
333 u32 precharge_to_activate, activate_to_precharge,
334 activate_to_readwrite, mcas_latency, refresh_recovery,
335 last_data_to_precharge, activate_to_activate,
336 last_write_data_to_read;
337 u32 timing_cfg_1;
338 /* DDR SDRAM Timing Configuration 2 register values */
339 u32 additive_latency, mcas_to_preamble_override, write_latency,
340 read_to_precharge, write_cmd_to_write_data,
341 minimum_cke_pulse_width, four_activates_window;
342 u32 timing_cfg_2;
343 /* DDR SDRAM Control Configuration register values */
344 u32 self_refresh, ecc, registered_dram, sdram_type,
345 dynamic_power_management, databus_width, nc_auto_precharge,
346 timing_2t, bank_interleaving_ctrl, precharge_bit_8, half_strength,
347 bypass_initialization;
348 u32 sdram_cfg;
349 /* DDR SDRAM Control Configuration 2 register values */
350 u32 force_self_refresh, dll_reset, dqs_config, odt_config,
351 posted_refreshes;
352 u32 sdram_cfg2;
353 /* DDR SDRAM Mode Configuration register values */
354 u32 sdmode, esdmode;
355 u32 sdram_mode;
356 /* DDR SDRAM Mode Configuration 2 register values */
357 u32 esdmode2, esdmode3;
358 u32 sdram_mode2;
359 /* DDR SDRAM Interval Configuration register values */
360 u32 refresh_interval, precharge_interval;
361 u32 sdram_interval;
362
363 priv->total_size = 0;
364
365 /* Disable both banks initially (might be re-enabled in loop below) */
366 out_be32(&im->ddr.cs_config[0], 0);
367 out_be32(&im->ddr.cs_config[1], 0);
368
369 dso = dev_read_u32_default(dev, "driver_software_override", 0);
370 if (dso > 1) {
371 debug("%s: driver_software_override value %d invalid.\n",
372 dev->name, dso);
373 return -EINVAL;
374 }
375
376 pz_override = dev_read_u32_default(dev, "p_impedance_override", 0);
377
378 switch (pz_override) {
379 case DSO_P_IMPEDANCE_HIGHEST_Z:
380 case DSO_P_IMPEDANCE_MUCH_HIGHER_Z:
381 case DSO_P_IMPEDANCE_HIGHER_Z:
382 case DSO_P_IMPEDANCE_NOMINAL:
383 case DSO_P_IMPEDANCE_LOWER_Z:
384 break;
385 default:
386 debug("%s: p_impedance_override value %d invalid.\n",
387 dev->name, pz_override);
388 return -EINVAL;
389 }
390
391 nz_override = dev_read_u32_default(dev, "n_impedance_override", 0);
392
393 switch (nz_override) {
394 case DSO_N_IMPEDANCE_HIGHEST_Z:
395 case DSO_N_IMPEDANCE_MUCH_HIGHER_Z:
396 case DSO_N_IMPEDANCE_HIGHER_Z:
397 case DSO_N_IMPEDANCE_NOMINAL:
398 case DSO_N_IMPEDANCE_LOWER_Z:
399 break;
400 default:
401 debug("%s: n_impedance_override value %d invalid.\n",
402 dev->name, nz_override);
403 return -EINVAL;
404 }
405
406 odt_term = dev_read_u32_default(dev, "odt_termination_value", 0);
407 if (odt_term > 1) {
408 debug("%s: odt_termination_value value %d invalid.\n",
409 dev->name, odt_term);
410 return -EINVAL;
411 }
412
413 ddr_type = dev_read_u32_default(dev, "ddr_type", 0);
414 if (ddr_type > 1) {
415 debug("%s: ddr_type value %d invalid.\n",
416 dev->name, ddr_type);
417 return -EINVAL;
418 }
419
420 mvref_sel = dev_read_u32_default(dev, "mvref_sel", 0);
421 if (mvref_sel > 1) {
422 debug("%s: mvref_sel value %d invalid.\n",
423 dev->name, mvref_sel);
424 return -EINVAL;
425 }
426
427 m_odr = dev_read_u32_default(dev, "m_odr", 0);
428 if (mvref_sel > 1) {
429 debug("%s: m_odr value %d invalid.\n",
430 dev->name, m_odr);
431 return -EINVAL;
432 }
433
434 ddrcdr = dso << (31 - 1) |
435 pz_override << (31 - 5) |
436 nz_override << (31 - 9) |
437 odt_term << (31 - 12) |
438 ddr_type << (31 - 13) |
439 mvref_sel << (31 - 29) |
440 m_odr << (31 - 30) | 1;
441
442 /* Configure the DDR control driver register */
443 out_be32(&im->sysconf.ddrcdr, ddrcdr);
444
445 dev_for_each_subnode(subnode, dev) {
446 u32 val[3];
447 u32 cs, addr, size;
448
449 /* CS, map address, size -> three values */
450 ofnode_read_u32_array(subnode, "reg", val, 3);
451
452 cs = val[0];
453 addr = val[1];
454 size = val[2];
455
456 if (cs > 1) {
457 debug("%s: chip select value %d invalid.\n",
458 dev->name, cs);
459 return -EINVAL;
460 }
461
462 /* TODO([email protected]): Sanity check for size. */
463
464 if (ofnode_read_bool(subnode, "read-spd"))
465 ret = mpc83xx_sdram_spd_init(subnode, cs, addr, size);
466 else
467 ret = mpc83xx_sdram_static_init(subnode, cs, addr,
468 size);
469 if (ret) {
470 debug("%s: RAM init failed.\n", dev->name);
471 return ret;
472 }
473 };
474
475 /*
476 * TODO([email protected]): This should only occur for static
477 * configuration
478 */
479
480 clock_adjust = dev_read_u32_default(dev, "clock_adjust", 0);
481 switch (clock_adjust) {
482 case CLOCK_ADJUST_025:
483 case CLOCK_ADJUST_05:
484 case CLOCK_ADJUST_075:
485 case CLOCK_ADJUST_1:
486 break;
487 default:
488 debug("%s: clock_adjust value %d invalid.\n",
489 dev->name, clock_adjust);
490 return -EINVAL;
491 }
492
493 /* Configure the DDR SDRAM Clock Control register */
494 out_be32(&im->ddr.sdram_clk_cntl, clock_adjust);
495
496 ext_refresh_rec = dev_read_u32_default(dev, "ext_refresh_rec", 0);
497 switch (ext_refresh_rec) {
498 case 0:
499 ext_refresh_rec_mask = 0 << TIMING_CFG3_EXT_REFREC_SHIFT;
500 break;
501 case 16:
502 ext_refresh_rec_mask = 1 << TIMING_CFG3_EXT_REFREC_SHIFT;
503 break;
504 case 32:
505 ext_refresh_rec_mask = 2 << TIMING_CFG3_EXT_REFREC_SHIFT;
506 break;
507 case 48:
508 ext_refresh_rec_mask = 3 << TIMING_CFG3_EXT_REFREC_SHIFT;
509 break;
510 case 64:
511 ext_refresh_rec_mask = 4 << TIMING_CFG3_EXT_REFREC_SHIFT;
512 break;
513 case 80:
514 ext_refresh_rec_mask = 5 << TIMING_CFG3_EXT_REFREC_SHIFT;
515 break;
516 case 96:
517 ext_refresh_rec_mask = 6 << TIMING_CFG3_EXT_REFREC_SHIFT;
518 break;
519 case 112:
520 ext_refresh_rec_mask = 7 << TIMING_CFG3_EXT_REFREC_SHIFT;
521 break;
522 default:
523 debug("%s: ext_refresh_rec value %d invalid.\n",
524 dev->name, ext_refresh_rec);
525 return -EINVAL;
526 }
527
528 /* Configure the DDR SDRAM Timing Configuration 3 register */
529 out_be32(&im->ddr.timing_cfg_3, ext_refresh_rec_mask);
530
531 read_to_write = dev_read_u32_default(dev, "read_to_write", 0);
532 if (read_to_write > 3) {
533 debug("%s: read_to_write value %d invalid.\n",
534 dev->name, read_to_write);
535 return -EINVAL;
536 }
537
538 write_to_read = dev_read_u32_default(dev, "write_to_read", 0);
539 if (write_to_read > 3) {
540 debug("%s: write_to_read value %d invalid.\n",
541 dev->name, write_to_read);
542 return -EINVAL;
543 }
544
545 read_to_read = dev_read_u32_default(dev, "read_to_read", 0);
546 if (read_to_read > 3) {
547 debug("%s: read_to_read value %d invalid.\n",
548 dev->name, read_to_read);
549 return -EINVAL;
550 }
551
552 write_to_write = dev_read_u32_default(dev, "write_to_write", 0);
553 if (write_to_write > 3) {
554 debug("%s: write_to_write value %d invalid.\n",
555 dev->name, write_to_write);
556 return -EINVAL;
557 }
558
559 active_powerdown_exit =
560 dev_read_u32_default(dev, "active_powerdown_exit", 0);
561 if (active_powerdown_exit > 7) {
562 debug("%s: active_powerdown_exit value %d invalid.\n",
563 dev->name, active_powerdown_exit);
564 return -EINVAL;
565 }
566
567 precharge_powerdown_exit =
568 dev_read_u32_default(dev, "precharge_powerdown_exit", 0);
569 if (precharge_powerdown_exit > 7) {
570 debug("%s: precharge_powerdown_exit value %d invalid.\n",
571 dev->name, precharge_powerdown_exit);
572 return -EINVAL;
573 }
574
575 odt_powerdown_exit = dev_read_u32_default(dev, "odt_powerdown_exit", 0);
576 if (odt_powerdown_exit > 15) {
577 debug("%s: odt_powerdown_exit value %d invalid.\n",
578 dev->name, odt_powerdown_exit);
579 return -EINVAL;
580 }
581
582 mode_reg_set_cycle = dev_read_u32_default(dev, "mode_reg_set_cycle", 0);
583 if (mode_reg_set_cycle > 15) {
584 debug("%s: mode_reg_set_cycle value %d invalid.\n",
585 dev->name, mode_reg_set_cycle);
586 return -EINVAL;
587 }
588
589 timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT |
590 write_to_read << TIMING_CFG0_WRT_SHIFT |
591 read_to_read << TIMING_CFG0_RRT_SHIFT |
592 write_to_write << TIMING_CFG0_WWT_SHIFT |
593 active_powerdown_exit << TIMING_CFG0_ACT_PD_EXIT_SHIFT |
594 precharge_powerdown_exit << TIMING_CFG0_PRE_PD_EXIT_SHIFT |
595 odt_powerdown_exit << TIMING_CFG0_ODT_PD_EXIT_SHIFT |
596 mode_reg_set_cycle << TIMING_CFG0_MRS_CYC_SHIFT;
597
598 out_be32(&im->ddr.timing_cfg_0, timing_cfg_0);
599
600 precharge_to_activate =
601 dev_read_u32_default(dev, "precharge_to_activate", 0);
602 if (precharge_to_activate > 7 || precharge_to_activate == 0) {
603 debug("%s: precharge_to_activate value %d invalid.\n",
604 dev->name, precharge_to_activate);
605 return -EINVAL;
606 }
607
608 activate_to_precharge =
609 dev_read_u32_default(dev, "activate_to_precharge", 0);
610 if (activate_to_precharge > 19) {
611 debug("%s: activate_to_precharge value %d invalid.\n",
612 dev->name, activate_to_precharge);
613 return -EINVAL;
614 }
615
616 activate_to_readwrite =
617 dev_read_u32_default(dev, "activate_to_readwrite", 0);
618 if (activate_to_readwrite > 7 || activate_to_readwrite == 0) {
619 debug("%s: activate_to_readwrite value %d invalid.\n",
620 dev->name, activate_to_readwrite);
621 return -EINVAL;
622 }
623
624 mcas_latency = dev_read_u32_default(dev, "mcas_latency", 0);
625 switch (mcas_latency) {
626 case CASLAT_20:
627 case CASLAT_25:
628 if (!IS_ENABLED(CONFIG_ARCH_MPC8308)) {
629 debug("%s: MCAS latency < 3.0 unsupported on MPC8308\n",
630 dev->name);
631 return -EINVAL;
632 }
633 /* fall through */
634 case CASLAT_30:
635 case CASLAT_35:
636 case CASLAT_40:
637 case CASLAT_45:
638 case CASLAT_50:
639 case CASLAT_55:
640 case CASLAT_60:
641 case CASLAT_65:
642 case CASLAT_70:
643 case CASLAT_75:
644 case CASLAT_80:
645 break;
646 default:
647 debug("%s: mcas_latency value %d invalid.\n",
648 dev->name, mcas_latency);
649 return -EINVAL;
650 }
651
652 refresh_recovery = dev_read_u32_default(dev, "refresh_recovery", 0);
653 if (refresh_recovery > 23 || refresh_recovery < 8) {
654 debug("%s: refresh_recovery value %d invalid.\n",
655 dev->name, refresh_recovery);
656 return -EINVAL;
657 }
658
659 last_data_to_precharge =
660 dev_read_u32_default(dev, "last_data_to_precharge", 0);
661 if (last_data_to_precharge > 7 || last_data_to_precharge == 0) {
662 debug("%s: last_data_to_precharge value %d invalid.\n",
663 dev->name, last_data_to_precharge);
664 return -EINVAL;
665 }
666
667 activate_to_activate =
668 dev_read_u32_default(dev, "activate_to_activate", 0);
669 if (activate_to_activate > 7 || activate_to_activate == 0) {
670 debug("%s: activate_to_activate value %d invalid.\n",
671 dev->name, activate_to_activate);
672 return -EINVAL;
673 }
674
675 last_write_data_to_read =
676 dev_read_u32_default(dev, "last_write_data_to_read", 0);
677 if (last_write_data_to_read > 7 || last_write_data_to_read == 0) {
678 debug("%s: last_write_data_to_read value %d invalid.\n",
679 dev->name, last_write_data_to_read);
680 return -EINVAL;
681 }
682
683 timing_cfg_1 = precharge_to_activate << TIMING_CFG1_PRETOACT_SHIFT |
684 (activate_to_precharge > 15 ?
685 activate_to_precharge - 16 :
686 activate_to_precharge) << TIMING_CFG1_ACTTOPRE_SHIFT |
687 activate_to_readwrite << TIMING_CFG1_ACTTORW_SHIFT |
688 mcas_latency << TIMING_CFG1_CASLAT_SHIFT |
689 (refresh_recovery - 8) << TIMING_CFG1_REFREC_SHIFT |
690 last_data_to_precharge << TIMING_CFG1_WRREC_SHIFT |
691 activate_to_activate << TIMING_CFG1_ACTTOACT_SHIFT |
692 last_write_data_to_read << TIMING_CFG1_WRTORD_SHIFT;
693
694 /* Configure the DDR SDRAM Timing Configuration 1 register */
695 out_be32(&im->ddr.timing_cfg_1, timing_cfg_1);
696
697 additive_latency = dev_read_u32_default(dev, "additive_latency", 0);
698 if (additive_latency > 5) {
699 debug("%s: additive_latency value %d invalid.\n",
700 dev->name, additive_latency);
701 return -EINVAL;
702 }
703
704 mcas_to_preamble_override =
705 dev_read_u32_default(dev, "mcas_to_preamble_override", 0);
706 switch (mcas_to_preamble_override) {
707 case READ_LAT_PLUS_1:
708 case READ_LAT:
709 case READ_LAT_PLUS_1_4:
710 case READ_LAT_PLUS_1_2:
711 case READ_LAT_PLUS_3_4:
712 case READ_LAT_PLUS_5_4:
713 case READ_LAT_PLUS_3_2:
714 case READ_LAT_PLUS_7_4:
715 case READ_LAT_PLUS_2:
716 case READ_LAT_PLUS_9_4:
717 case READ_LAT_PLUS_5_2:
718 case READ_LAT_PLUS_11_4:
719 case READ_LAT_PLUS_3:
720 case READ_LAT_PLUS_13_4:
721 case READ_LAT_PLUS_7_2:
722 case READ_LAT_PLUS_15_4:
723 case READ_LAT_PLUS_4:
724 case READ_LAT_PLUS_17_4:
725 case READ_LAT_PLUS_9_2:
726 case READ_LAT_PLUS_19_4:
727 break;
728 default:
729 debug("%s: mcas_to_preamble_override value %d invalid.\n",
730 dev->name, mcas_to_preamble_override);
731 return -EINVAL;
732 }
733
734 write_latency = dev_read_u32_default(dev, "write_latency", 0);
735 if (write_latency > 7 || write_latency == 0) {
736 debug("%s: write_latency value %d invalid.\n",
737 dev->name, write_latency);
738 return -EINVAL;
739 }
740
741 read_to_precharge = dev_read_u32_default(dev, "read_to_precharge", 0);
742 if (read_to_precharge > 4 || read_to_precharge == 0) {
743 debug("%s: read_to_precharge value %d invalid.\n",
744 dev->name, read_to_precharge);
745 return -EINVAL;
746 }
747
748 write_cmd_to_write_data =
749 dev_read_u32_default(dev, "write_cmd_to_write_data", 0);
750 switch (write_cmd_to_write_data) {
751 case CLOCK_DELAY_0:
752 case CLOCK_DELAY_1_4:
753 case CLOCK_DELAY_1_2:
754 case CLOCK_DELAY_3_4:
755 case CLOCK_DELAY_1:
756 case CLOCK_DELAY_5_4:
757 case CLOCK_DELAY_3_2:
758 break;
759 default:
760 debug("%s: write_cmd_to_write_data value %d invalid.\n",
761 dev->name, write_cmd_to_write_data);
762 return -EINVAL;
763 }
764
765 minimum_cke_pulse_width =
766 dev_read_u32_default(dev, "minimum_cke_pulse_width", 0);
767 if (minimum_cke_pulse_width > 4 || minimum_cke_pulse_width == 0) {
768 debug("%s: minimum_cke_pulse_width value %d invalid.\n",
769 dev->name, minimum_cke_pulse_width);
770 return -EINVAL;
771 }
772
773 four_activates_window =
774 dev_read_u32_default(dev, "four_activates_window", 0);
775 if (four_activates_window > 20 || four_activates_window == 0) {
776 debug("%s: four_activates_window value %d invalid.\n",
777 dev->name, four_activates_window);
778 return -EINVAL;
779 }
780
781 timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT |
782 mcas_to_preamble_override << TIMING_CFG2_CPO_SHIFT |
783 write_latency << TIMING_CFG2_WR_LAT_DELAY_SHIFT |
784 read_to_precharge << TIMING_CFG2_RD_TO_PRE_SHIFT |
785 write_cmd_to_write_data << TIMING_CFG2_WR_DATA_DELAY_SHIFT |
786 minimum_cke_pulse_width << TIMING_CFG2_CKE_PLS_SHIFT |
787 four_activates_window << TIMING_CFG2_FOUR_ACT_SHIFT;
788
789 out_be32(&im->ddr.timing_cfg_2, timing_cfg_2);
790
791 self_refresh = dev_read_u32_default(dev, "self_refresh", 0);
792 switch (self_refresh) {
793 case SREN_DISABLE:
794 case SREN_ENABLE:
795 break;
796 default:
797 debug("%s: self_refresh value %d invalid.\n",
798 dev->name, self_refresh);
799 return -EINVAL;
800 }
801
802 ecc = dev_read_u32_default(dev, "ecc", 0);
803 switch (ecc) {
804 case ECC_DISABLE:
805 case ECC_ENABLE:
806 break;
807 default:
808 debug("%s: ecc value %d invalid.\n", dev->name, ecc);
809 return -EINVAL;
810 }
811
812 registered_dram = dev_read_u32_default(dev, "registered_dram", 0);
813 switch (registered_dram) {
814 case RD_DISABLE:
815 case RD_ENABLE:
816 break;
817 default:
818 debug("%s: registered_dram value %d invalid.\n",
819 dev->name, registered_dram);
820 return -EINVAL;
821 }
822
823 sdram_type = dev_read_u32_default(dev, "sdram_type", 0);
824 switch (sdram_type) {
825 case TYPE_DDR1:
826 case TYPE_DDR2:
827 break;
828 default:
829 debug("%s: sdram_type value %d invalid.\n",
830 dev->name, sdram_type);
831 return -EINVAL;
832 }
833
834 dynamic_power_management =
835 dev_read_u32_default(dev, "dynamic_power_management", 0);
836 switch (dynamic_power_management) {
837 case DYN_PWR_DISABLE:
838 case DYN_PWR_ENABLE:
839 break;
840 default:
841 debug("%s: dynamic_power_management value %d invalid.\n",
842 dev->name, dynamic_power_management);
843 return -EINVAL;
844 }
845
846 databus_width = dev_read_u32_default(dev, "databus_width", 0);
847 switch (databus_width) {
848 case DATA_BUS_WIDTH_16:
849 case DATA_BUS_WIDTH_32:
850 break;
851 default:
852 debug("%s: databus_width value %d invalid.\n",
853 dev->name, databus_width);
854 return -EINVAL;
855 }
856
857 nc_auto_precharge = dev_read_u32_default(dev, "nc_auto_precharge", 0);
858 switch (nc_auto_precharge) {
859 case NCAP_DISABLE:
860 case NCAP_ENABLE:
861 break;
862 default:
863 debug("%s: nc_auto_precharge value %d invalid.\n",
864 dev->name, nc_auto_precharge);
865 return -EINVAL;
866 }
867
868 timing_2t = dev_read_u32_default(dev, "timing_2t", 0);
869 switch (timing_2t) {
870 case TIMING_1T:
871 case TIMING_2T:
872 break;
873 default:
874 debug("%s: timing_2t value %d invalid.\n",
875 dev->name, timing_2t);
876 return -EINVAL;
877 }
878
879 bank_interleaving_ctrl =
880 dev_read_u32_default(dev, "bank_interleaving_ctrl", 0);
881 switch (bank_interleaving_ctrl) {
882 case INTERLEAVE_NONE:
883 case INTERLEAVE_1_AND_2:
884 break;
885 default:
886 debug("%s: bank_interleaving_ctrl value %d invalid.\n",
887 dev->name, bank_interleaving_ctrl);
888 return -EINVAL;
889 }
890
891 precharge_bit_8 = dev_read_u32_default(dev, "precharge_bit_8", 0);
892 switch (precharge_bit_8) {
893 case PRECHARGE_MA_10:
894 case PRECHARGE_MA_8:
895 break;
896 default:
897 debug("%s: precharge_bit_8 value %d invalid.\n",
898 dev->name, precharge_bit_8);
899 return -EINVAL;
900 }
901
902 half_strength = dev_read_u32_default(dev, "half_strength", 0);
903 switch (half_strength) {
904 case STRENGTH_FULL:
905 case STRENGTH_HALF:
906 break;
907 default:
908 debug("%s: half_strength value %d invalid.\n",
909 dev->name, half_strength);
910 return -EINVAL;
911 }
912
913 bypass_initialization =
914 dev_read_u32_default(dev, "bypass_initialization", 0);
915 switch (bypass_initialization) {
916 case INITIALIZATION_DONT_BYPASS:
917 case INITIALIZATION_BYPASS:
918 break;
919 default:
920 debug("%s: bypass_initialization value %d invalid.\n",
921 dev->name, bypass_initialization);
922 return -EINVAL;
923 }
924
925 sdram_cfg = self_refresh << SDRAM_CFG_SREN_SHIFT |
926 ecc << SDRAM_CFG_ECC_EN_SHIFT |
927 registered_dram << SDRAM_CFG_RD_EN_SHIFT |
928 sdram_type << SDRAM_CFG_SDRAM_TYPE_SHIFT |
929 dynamic_power_management << SDRAM_CFG_DYN_PWR_SHIFT |
930 databus_width << SDRAM_CFG_DBW_SHIFT |
931 nc_auto_precharge << SDRAM_CFG_NCAP_SHIFT |
932 timing_2t << SDRAM_CFG_2T_EN_SHIFT |
933 bank_interleaving_ctrl << SDRAM_CFG_BA_INTLV_CTL_SHIFT |
934 precharge_bit_8 << SDRAM_CFG_PCHB8_SHIFT |
935 half_strength << SDRAM_CFG_HSE_SHIFT |
936 bypass_initialization << SDRAM_CFG_BI_SHIFT;
937
938 out_be32(&im->ddr.sdram_cfg, sdram_cfg);
939
940 force_self_refresh = dev_read_u32_default(dev, "force_self_refresh", 0);
941 switch (force_self_refresh) {
942 case MODE_NORMAL:
943 case MODE_REFRESH:
944 break;
945 default:
946 debug("%s: force_self_refresh value %d invalid.\n",
947 dev->name, force_self_refresh);
948 return -EINVAL;
949 }
950
951 dll_reset = dev_read_u32_default(dev, "dll_reset", 0);
952 switch (dll_reset) {
953 case DLL_RESET_ENABLE:
954 case DLL_RESET_DISABLE:
955 break;
956 default:
957 debug("%s: dll_reset value %d invalid.\n",
958 dev->name, dll_reset);
959 return -EINVAL;
960 }
961
962 dqs_config = dev_read_u32_default(dev, "dqs_config", 0);
963 switch (dqs_config) {
964 case DQS_TRUE:
965 break;
966 default:
967 debug("%s: dqs_config value %d invalid.\n",
968 dev->name, dqs_config);
969 return -EINVAL;
970 }
971
972 odt_config = dev_read_u32_default(dev, "odt_config", 0);
973 switch (odt_config) {
974 case ODT_ASSERT_NEVER:
975 case ODT_ASSERT_WRITES:
976 case ODT_ASSERT_READS:
977 case ODT_ASSERT_ALWAYS:
978 break;
979 default:
980 debug("%s: odt_config value %d invalid.\n",
981 dev->name, odt_config);
982 return -EINVAL;
983 }
984
985 posted_refreshes = dev_read_u32_default(dev, "posted_refreshes", 0);
986 if (posted_refreshes > 8 || posted_refreshes == 0) {
987 debug("%s: posted_refreshes value %d invalid.\n",
988 dev->name, posted_refreshes);
989 return -EINVAL;
990 }
991
992 sdram_cfg2 = force_self_refresh << SDRAM_CFG2_FRC_SR_SHIFT |
993 dll_reset << SDRAM_CFG2_DLL_RST_DIS |
994 dqs_config << SDRAM_CFG2_DQS_CFG |
995 odt_config << SDRAM_CFG2_ODT_CFG |
996 posted_refreshes << SDRAM_CFG2_NUM_PR;
997
998 out_be32(&im->ddr.sdram_cfg2, sdram_cfg2);
999
1000 sdmode = dev_read_u32_default(dev, "sdmode", 0);
1001 if (sdmode > 0xFFFF) {
1002 debug("%s: sdmode value %d invalid.\n",
1003 dev->name, sdmode);
1004 return -EINVAL;
1005 }
1006
1007 esdmode = dev_read_u32_default(dev, "esdmode", 0);
1008 if (esdmode > 0xFFFF) {
1009 debug("%s: esdmode value %d invalid.\n", dev->name, esdmode);
1010 return -EINVAL;
1011 }
1012
1013 sdram_mode = sdmode << SDRAM_MODE_SD_SHIFT |
1014 esdmode << SDRAM_MODE_ESD_SHIFT;
1015
1016 out_be32(&im->ddr.sdram_mode, sdram_mode);
1017
1018 esdmode2 = dev_read_u32_default(dev, "esdmode2", 0);
1019 if (esdmode2 > 0xFFFF) {
1020 debug("%s: esdmode2 value %d invalid.\n", dev->name, esdmode2);
1021 return -EINVAL;
1022 }
1023
1024 esdmode3 = dev_read_u32_default(dev, "esdmode3", 0);
1025 if (esdmode3 > 0xFFFF) {
1026 debug("%s: esdmode3 value %d invalid.\n", dev->name, esdmode3);
1027 return -EINVAL;
1028 }
1029
1030 sdram_mode2 = esdmode2 << SDRAM_MODE2_ESD2_SHIFT |
1031 esdmode3 << SDRAM_MODE2_ESD3_SHIFT;
1032
1033 out_be32(&im->ddr.sdram_mode2, sdram_mode2);
1034
1035 refresh_interval = dev_read_u32_default(dev, "refresh_interval", 0);
1036 if (refresh_interval > 0xFFFF) {
1037 debug("%s: refresh_interval value %d invalid.\n",
1038 dev->name, refresh_interval);
1039 return -EINVAL;
1040 }
1041
1042 precharge_interval = dev_read_u32_default(dev, "precharge_interval", 0);
1043 if (precharge_interval > 0x3FFF) {
1044 debug("%s: precharge_interval value %d invalid.\n",
1045 dev->name, precharge_interval);
1046 return -EINVAL;
1047 }
1048
1049 sdram_interval = refresh_interval << SDRAM_INTERVAL_REFINT_SHIFT |
1050 precharge_interval << SDRAM_INTERVAL_BSTOPRE_SHIFT;
1051
1052 out_be32(&im->ddr.sdram_interval, sdram_interval);
1053 sync();
1054
1055 /* Enable DDR controller */
1056 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
1057 sync();
1058
1059 dev_for_each_subnode(subnode, dev) {
1060 u32 val[3];
1061 u32 addr, size;
1062
1063 /* CS, map address, size -> three values */
1064 ofnode_read_u32_array(subnode, "reg", val, 3);
1065
1066 addr = val[1];
1067 size = val[2];
1068
1069 priv->total_size += get_ram_size((long int *)addr, size);
1070 };
1071
1072 gd->ram_size = priv->total_size;
1073
1074 return 0;
1075}
1076
1077static int mpc83xx_sdram_get_info(struct udevice *dev, struct ram_info *info)
1078{
1079 /* TODO([email protected]): Implement */
1080 return 0;
1081}
1082
1083static struct ram_ops mpc83xx_sdram_ops = {
1084 .get_info = mpc83xx_sdram_get_info,
1085};
1086
1087static const struct udevice_id mpc83xx_sdram_ids[] = {
1088 { .compatible = "fsl,mpc83xx-mem-controller" },
1089 { /* sentinel */ }
1090};
1091
1092U_BOOT_DRIVER(mpc83xx_sdram) = {
1093 .name = "mpc83xx_sdram",
1094 .id = UCLASS_RAM,
1095 .of_match = mpc83xx_sdram_ids,
1096 .ops = &mpc83xx_sdram_ops,
d1998a9f 1097 .of_to_plat = mpc83xx_sdram_of_to_plat,
e4061556 1098 .probe = mpc83xx_sdram_probe,
41575d8e 1099 .priv_auto = sizeof(struct mpc83xx_sdram_priv),
e4061556 1100};
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