[J-u-boot.git] / arch / riscv / cpu / ax25 / Kconfig

config RISCV_NDS
	bool
	select ARCH_EARLY_INIT_R
	imply CPU
	imply CPU_RISCV
	imply RISCV_TIMER
	imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
	imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
	help
	  Run U-Boot on AndeStar V5 platforms and use some specific features
	  which are provided by Andes Technology AndeStar V5 families.

if RISCV_NDS

config RISCV_NDS_CACHE
	bool "AndeStar V5 families specific cache support"
	depends on RISCV_MMODE || SPL_RISCV_MMODE
	help
	  Provide Andes Technology AndeStar V5 families specific cache support.

endif
Commit	Line	Data
52923c6d	1	config RISCV_NDS
44fe795c	2	bool
8848474c RC	3	select ARCH_EARLY_INIT_R
	4	imply CPU
	5	imply CPU_RISCV
	6	imply RISCV_TIMER
fbfd92bf LA	7	imply ANDES_PLIC if (RISCV_MMODE \|\| SPL_RISCV_MMODE)
fbfd92bf LA	8	imply ANDES_PLMT if (RISCV_MMODE \|\| SPL_RISCV_MMODE)
52923c6d	9	help
44fe795c BM	10	Run U-Boot on AndeStar V5 platforms and use some specific features
	11	which are provided by Andes Technology AndeStar V5 families.
	12
	13	if RISCV_NDS
	14
	15	config RISCV_NDS_CACHE
	16	bool "AndeStar V5 families specific cache support"
fbfd92bf	17	depends on RISCV_MMODE \|\| SPL_RISCV_MMODE
44fe795c BM	18	help
	19	Provide Andes Technology AndeStar V5 families specific cache support.
	20
	21	endif