projects / J-u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| ae41d6aa WD |
1 | #ifndef __64260_H__ |
| 2 | #define __64260_H__ | |
| 3 | ||
| 4 | /* CPU Configuration bits */ | |
| 5 | #define CPU_CONF_ADDR_MISS_EN (1 << 8) | |
| 6 | #define CPU_CONF_AACK_DELAY (1 << 11) | |
| 7 | #define CPU_CONF_ENDIANESS (1 << 12) | |
| 8 | #define CPU_CONF_PIPELINE (1 << 13) | |
| 9 | #define CPU_CONF_TA_DELAY (1 << 15) | |
| 10 | #define CPU_CONF_RD_OOO (1 << 16) | |
| 11 | #define CPU_CONF_STOP_RETRY (1 << 17) | |
| 12 | #define CPU_CONF_MULTI_DECODE (1 << 18) | |
| 13 | #define CPU_CONF_DP_VALID (1 << 19) | |
| 14 | #define CPU_CONF_PERR_PROP (1 << 22) | |
| 15 | #define CPU_CONF_FAST_CLK (1 << 23) | |
| 16 | #define CPU_CONF_AACK_DELAY_2 (1 << 25) | |
| 17 | #define CPU_CONF_AP_VALID (1 << 26) | |
| 18 | #define CPU_CONF_REMAP_WR_DIS (1 << 27) | |
| 19 | #define CPU_CONF_CONF_SB_DIS (1 << 28) | |
| 20 | #define CPU_CONF_IO_SB_DIS (1 << 29) | |
| 21 | #define CPU_CONF_CLK_SYNC (1 << 30) | |
| 22 | ||
| 23 | /* CPU Master Control bits */ | |
| 24 | #define CPU_MAST_CTL_ARB_EN (1 << 8) | |
| 25 | #define CPU_MAST_CTL_MASK_BR_1 (1 << 9) | |
| 26 | #define CPU_MAST_CTL_M_WR_TRIG (1 << 10) | |
| 27 | #define CPU_MAST_CTL_M_RD_TRIG (1 << 11) | |
| 28 | #define CPU_MAST_CTL_CLEAN_BLK (1 << 12) | |
| 29 | #define CPU_MAST_CTL_FLUSH_BLK (1 << 13) | |
| 30 | ||
| 31 | #endif /* __64260_H__ */ |