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Fix endianess conversion in usb_ohci.c
[J-u-boot.git] / drivers / usb / usb_ohci.c
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3e326ece 1/*
4dae14ce
ZW		 2 * URB OHCI HCD (Host Controller Driver) for USB on the AT91RM9200 and PCI bus.
3 *
4 * Interrupt support is added. Now, it has been tested
5 * on ULI1575 chip and works well with USB keyboard.
6 *
7 * (C) Copyright 2007
8 * Zhang Wei, Freescale Semiconductor, Inc. <[email protected]>
3e326ece
MK		 9 *
10 * (C) Copyright 2003
11 * Gary Jennejohn, DENX Software Engineering <[email protected]>
12 *
13 * Note: Much of this code has been derived from Linux 2.4
14 * (C) Copyright 1999 Roman Weissgaerber <[email protected]>
15 * (C) Copyright 2000-2002 David Brownell
16 *
17 * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
18 * [email protected] - based on s3c24x0's driver
19 *
20 * See file CREDITS for list of people who contributed to this
21 * project.
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License as
25 * published by the Free Software Foundation; either version 2 of
26 * the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
ddf83a2f 30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3e326ece
MK		 31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
36 * MA 02111-1307 USA
37 *
38 */
39/*
40 * IMPORTANT NOTES
fc43be47 41 * 1 - Read doc/README.generic_usb_ohci
3e326ece 42 * 2 - this driver is intended for use with USB Mass Storage Devices
4dae14ce 43 * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
fc43be47 44 * 2 - when running on a PQFP208 AT91RM9200, define CONFIG_AT91C_PQFP_UHPBUG
3e326ece
MK		 45 * to activate workaround for bug #41 or this driver will NOT work!
46 */
47
48#include <common.h>
3e326ece 49
7b59b3c7 50#ifdef CONFIG_USB_OHCI_NEW
3e326ece 51
fc43be47
MK		 52#include <asm/byteorder.h>
53
54#if defined(CONFIG_PCI_OHCI)
4dae14ce 55# include <pci.h>
477434c6
SP		 56#if !defined(CONFIG_PCI_OHCI_DEVNO)
57#define CONFIG_PCI_OHCI_DEVNO 0
58#endif
ddf83a2f 59#endif
3e326ece
MK		 60
61#include <malloc.h>
62#include <usb.h>
63#include "usb_ohci.h"
64
e8da58f2
WD		 65#ifdef CONFIG_AT91RM9200
66#include <asm/arch/hardware.h> /* needed for AT91_USB_HOST_BASE */
67#endif
68
ddf83a2f
MK		 69#if defined(CONFIG_ARM920T) || \
70 defined(CONFIG_S3C2400) || \
ae3b770e
MK		 71 defined(CONFIG_S3C2410) || \
72 defined(CONFIG_440EP) || \
4dae14ce 73 defined(CONFIG_PCI_OHCI) || \
2596f5b9
SR		 74 defined(CONFIG_MPC5200) || \
75 defined(CFG_OHCI_USE_NPS)
24e37645
MK		 76# define OHCI_USE_NPS /* force NoPowerSwitching mode */
77#endif
78
3e326ece 79#undef OHCI_VERBOSE_DEBUG /* not always helpful */
ae3b770e
MK		 80#undef DEBUG
81#undef SHOW_INFO
82#undef OHCI_FILL_TRACE
3e326ece
MK		 83
84/* For initializing controller (mask in an HCFS mode too) */
85#define OHCI_CONTROL_INIT \
86 (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
87
fc43be47
MK		 88/*
89 * e.g. PCI controllers need this
90 */
91#ifdef CFG_OHCI_SWAP_REG_ACCESS
f957576c
MK		 92# define readl(a) __swap_32(*((volatile u32 *)(a)))
93# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
fc43be47 94#else
f957576c
MK		 95# define readl(a) (*((volatile u32 *)(a)))
96# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
fc43be47 97#endif /* CFG_OHCI_SWAP_REG_ACCESS */
3e326ece
MK		 98
99#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
100
4dae14ce
ZW		 101#ifdef CONFIG_PCI_OHCI
102static struct pci_device_id ohci_pci_ids[] = {
103 {0x10b9, 0x5237}, /* ULI1575 PCI OHCI module ids */
97213f32 104 {0x1033, 0x0035}, /* NEC PCI OHCI module ids */
3afac79e 105 {0x1131, 0x1561}, /* Philips 1561 PCI OHCI module ids */
4dae14ce
ZW		 106 /* Please add supported PCI OHCI controller ids here */
107 {0, 0}
108};
109#endif
110
3e326ece
MK		 111#ifdef DEBUG
112#define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
113#else
114#define dbg(format, arg...) do {} while(0)
115#endif /* DEBUG */
116#define err(format, arg...) printf("ERROR: " format "\n", ## arg)
3e326ece
MK		 117#ifdef SHOW_INFO
118#define info(format, arg...) printf("INFO: " format "\n", ## arg)
119#else
120#define info(format, arg...) do {} while(0)
121#endif
122
fc43be47
MK		 123#ifdef CFG_OHCI_BE_CONTROLLER
124# define m16_swap(x) cpu_to_be16(x)
125# define m32_swap(x) cpu_to_be32(x)
ae3b770e 126#else
fc43be47
MK		 127# define m16_swap(x) cpu_to_le16(x)
128# define m32_swap(x) cpu_to_le32(x)
129#endif /* CFG_OHCI_BE_CONTROLLER */
3e326ece
MK		 130
131/* global ohci_t */
132static ohci_t gohci;
133/* this must be aligned to a 256 byte boundary */
134struct ohci_hcca ghcca[1];
135/* a pointer to the aligned storage */
136struct ohci_hcca *phcca;
137/* this allocates EDs for all possible endpoints */
138struct ohci_device ohci_dev;
3e326ece
MK		 139/* RHSC flag */
140int got_rhsc;
141/* device which was disconnected */
142struct usb_device *devgone;
143
83fe3233
MK		 144static inline u32 roothub_a (struct ohci *hc)
145 { return readl (&hc->regs->roothub.a); }
3e326ece
MK		 146static inline u32 roothub_b (struct ohci *hc)
147 { return readl (&hc->regs->roothub.b); }
148static inline u32 roothub_status (struct ohci *hc)
149 { return readl (&hc->regs->roothub.status); }
83fe3233
MK		 150static inline u32 roothub_portstatus (struct ohci *hc, int i)
151 { return readl (&hc->regs->roothub.portstatus[i]); }
3e326ece 152
3e326ece
MK		 153/* forward declaration */
154static int hc_interrupt (void);
155static void
156td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
157 int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
158
159/*-------------------------------------------------------------------------*
160 * URB support functions
161 *-------------------------------------------------------------------------*/
162
163/* free HCD-private data associated with this URB */
164
165static void urb_free_priv (urb_priv_t * urb)
166{
167 int i;
168 int last;
169 struct td * td;
170
171 last = urb->length - 1;
172 if (last >= 0) {
173 for (i = 0; i <= last; i++) {
174 td = urb->td[i];
175 if (td) {
176 td->usb_dev = NULL;
177 urb->td[i] = NULL;
178 }
179 }
180 }
4dae14ce 181 free(urb);
3e326ece
MK		 182}
183
184/*-------------------------------------------------------------------------*/
185
186#ifdef DEBUG
187static int sohci_get_current_frame_number (struct usb_device * dev);
188
189/* debug| print the main components of an URB
190 * small: 0) header + data packets 1) just header */
191
4dae14ce
ZW		 192static void pkt_print (urb_priv_t *purb, struct usb_device * dev,
193 unsigned long pipe, void * buffer,
3e326ece
MK		 194 int transfer_len, struct devrequest * setup, char * str, int small)
195{
3e326ece
MK		 196 dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
197 str,
198 sohci_get_current_frame_number (dev),
199 usb_pipedevice (pipe),
200 usb_pipeendpoint (pipe),
201 usb_pipeout (pipe)? 'O': 'I',
202 usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
203 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
4dae14ce 204 (purb ? purb->actual_length : 0),
3e326ece
MK		 205 transfer_len, dev->status);
206#ifdef OHCI_VERBOSE_DEBUG
207 if (!small) {
208 int i, len;
209
210 if (usb_pipecontrol (pipe)) {
211 printf (__FILE__ ": cmd(8):");
212 for (i = 0; i < 8 ; i++)
213 printf (" %02x", ((__u8 *) setup) [i]);
214 printf ("\n");
215 }
216 if (transfer_len > 0 && buffer) {
217 printf (__FILE__ ": data(%d/%d):",
4dae14ce 218 (purb ? purb->actual_length : 0),
3e326ece
MK		 219 transfer_len);
220 len = usb_pipeout (pipe)?
4dae14ce
ZW		 221 transfer_len:
222 (purb ? purb->actual_length : 0);
3e326ece
MK		 223 for (i = 0; i < 16 && i < len; i++)
224 printf (" %02x", ((__u8 *) buffer) [i]);
225 printf ("%s\n", i < len? "...": "");
226 }
227 }
228#endif
229}
230
231/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
232void ep_print_int_eds (ohci_t *ohci, char * str) {
233 int i, j;
234 __u32 * ed_p;
235 for (i= 0; i < 32; i++) {
236 j = 5;
237 ed_p = &(ohci->hcca->int_table [i]);
238 if (*ed_p == 0)
239 continue;
240 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
241 while (*ed_p != 0 && j--) {
242 ed_t *ed = (ed_t *)m32_swap(ed_p);
243 printf (" ed: %4x;", ed->hwINFO);
244 ed_p = &ed->hwNextED;
245 }
246 printf ("\n");
247 }
248}
249
250static void ohci_dump_intr_mask (char *label, __u32 mask)
251{
252 dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
253 label,
254 mask,
255 (mask & OHCI_INTR_MIE) ? " MIE" : "",
256 (mask & OHCI_INTR_OC) ? " OC" : "",
257 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
258 (mask & OHCI_INTR_FNO) ? " FNO" : "",
259 (mask & OHCI_INTR_UE) ? " UE" : "",
260 (mask & OHCI_INTR_RD) ? " RD" : "",
261 (mask & OHCI_INTR_SF) ? " SF" : "",
262 (mask & OHCI_INTR_WDH) ? " WDH" : "",
263 (mask & OHCI_INTR_SO) ? " SO" : ""
264 );
265}
266
267static void maybe_print_eds (char *label, __u32 value)
268{
269 ed_t *edp = (ed_t *)value;
270
271 if (value) {
272 dbg ("%s %08x", label, value);
273 dbg ("%08x", edp->hwINFO);
274 dbg ("%08x", edp->hwTailP);
275 dbg ("%08x", edp->hwHeadP);
276 dbg ("%08x", edp->hwNextED);
277 }
278}
279
280static char * hcfs2string (int state)
281{
282 switch (state) {
283 case OHCI_USB_RESET: return "reset";
284 case OHCI_USB_RESUME: return "resume";
285 case OHCI_USB_OPER: return "operational";
286 case OHCI_USB_SUSPEND: return "suspend";
287 }
288 return "?";
289}
290
291/* dump control and status registers */
292static void ohci_dump_status (ohci_t *controller)
293{
294 struct ohci_regs *regs = controller->regs;
295 __u32 temp;
296
297 temp = readl (&regs->revision) & 0xff;
298 if (temp != 0x10)
299 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
300
301 temp = readl (&regs->control);
302 dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
303 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
304 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
305 (temp & OHCI_CTRL_IR) ? " IR" : "",
306 hcfs2string (temp & OHCI_CTRL_HCFS),
307 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
308 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
309 (temp & OHCI_CTRL_IE) ? " IE" : "",
310 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
311 temp & OHCI_CTRL_CBSR
312 );
313
314 temp = readl (&regs->cmdstatus);
315 dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
316 (temp & OHCI_SOC) >> 16,
317 (temp & OHCI_OCR) ? " OCR" : "",
318 (temp & OHCI_BLF) ? " BLF" : "",
319 (temp & OHCI_CLF) ? " CLF" : "",
320 (temp & OHCI_HCR) ? " HCR" : ""
321 );
322
323 ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
324 ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
325
326 maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
327
328 maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
329 maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
330
331 maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
332 maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
333
334 maybe_print_eds ("donehead", readl (&regs->donehead));
335}
336
337static void ohci_dump_roothub (ohci_t *controller, int verbose)
338{
339 __u32 temp, ndp, i;
340
341 temp = roothub_a (controller);
342 ndp = (temp & RH_A_NDP);
343#ifdef CONFIG_AT91C_PQFP_UHPBUG
344 ndp = (ndp == 2) ? 1:0;
3e326ece
MK		 345#endif
346 if (verbose) {
347 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
348 ((temp & RH_A_POTPGT) >> 24) & 0xff,
349 (temp & RH_A_NOCP) ? " NOCP" : "",
350 (temp & RH_A_OCPM) ? " OCPM" : "",
351 (temp & RH_A_DT) ? " DT" : "",
352 (temp & RH_A_NPS) ? " NPS" : "",
353 (temp & RH_A_PSM) ? " PSM" : "",
354 ndp
355 );
356 temp = roothub_b (controller);
357 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
358 temp,
359 (temp & RH_B_PPCM) >> 16,
360 (temp & RH_B_DR)
361 );
362 temp = roothub_status (controller);
363 dbg ("roothub.status: %08x%s%s%s%s%s%s",
364 temp,
365 (temp & RH_HS_CRWE) ? " CRWE" : "",
366 (temp & RH_HS_OCIC) ? " OCIC" : "",
367 (temp & RH_HS_LPSC) ? " LPSC" : "",
368 (temp & RH_HS_DRWE) ? " DRWE" : "",
369 (temp & RH_HS_OCI) ? " OCI" : "",
370 (temp & RH_HS_LPS) ? " LPS" : ""
371 );
372 }
373
374 for (i = 0; i < ndp; i++) {
375 temp = roothub_portstatus (controller, i);
376 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
377 i,
378 temp,
379 (temp & RH_PS_PRSC) ? " PRSC" : "",
380 (temp & RH_PS_OCIC) ? " OCIC" : "",
381 (temp & RH_PS_PSSC) ? " PSSC" : "",
382 (temp & RH_PS_PESC) ? " PESC" : "",
383 (temp & RH_PS_CSC) ? " CSC" : "",
384
385 (temp & RH_PS_LSDA) ? " LSDA" : "",
386 (temp & RH_PS_PPS) ? " PPS" : "",
387 (temp & RH_PS_PRS) ? " PRS" : "",
388 (temp & RH_PS_POCI) ? " POCI" : "",
389 (temp & RH_PS_PSS) ? " PSS" : "",
390
391 (temp & RH_PS_PES) ? " PES" : "",
392 (temp & RH_PS_CCS) ? " CCS" : ""
393 );
394 }
395}
396
397static void ohci_dump (ohci_t *controller, int verbose)
398{
399 dbg ("OHCI controller usb-%s state", controller->slot_name);
400
401 /* dumps some of the state we know about */
402 ohci_dump_status (controller);
403 if (verbose)
404 ep_print_int_eds (controller, "hcca");
405 dbg ("hcca frame #%04x", controller->hcca->frame_no);
406 ohci_dump_roothub (controller, 1);
2596f5b9 407}
3e326ece
MK		 408#endif /* DEBUG */
409
410/*-------------------------------------------------------------------------*
411 * Interface functions (URB)
412 *-------------------------------------------------------------------------*/
413
414/* get a transfer request */
415
4dae14ce 416int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup)
3e326ece
MK		 417{
418 ohci_t *ohci;
419 ed_t * ed;
4dae14ce 420 urb_priv_t *purb_priv = urb;
3e326ece 421 int i, size = 0;
4dae14ce
ZW		 422 struct usb_device *dev = urb->dev;
423 unsigned long pipe = urb->pipe;
424 void *buffer = urb->transfer_buffer;
425 int transfer_len = urb->transfer_buffer_length;
426 int interval = urb->interval;
3e326ece
MK		 427
428 ohci = &gohci;
429
430 /* when controller's hung, permit only roothub cleanup attempts
431 * such as powering down ports */
432 if (ohci->disabled) {
433 err("sohci_submit_job: EPIPE");
434 return -1;
435 }
ae79f606 436
ddf83a2f 437 /* we're about to begin a new transaction here so mark the URB unfinished */
4dae14ce 438 urb->finished = 0;
3e326ece
MK		 439
440 /* every endpoint has a ed, locate and fill it */
4dae14ce 441 if (!(ed = ep_add_ed (dev, pipe, interval, 1))) {
3e326ece
MK		 442 err("sohci_submit_job: ENOMEM");
443 return -1;
444 }
445
446 /* for the private part of the URB we need the number of TDs (size) */
447 switch (usb_pipetype (pipe)) {
448 case PIPE_BULK: /* one TD for every 4096 Byte */
449 size = (transfer_len - 1) / 4096 + 1;
450 break;
451 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
452 size = (transfer_len == 0)? 2:
453 (transfer_len - 1) / 4096 + 3;
454 break;
4dae14ce
ZW		 455 case PIPE_INTERRUPT: /* 1 TD */
456 size = 1;
457 break;
3e326ece
MK		 458 }
459
4dae14ce
ZW		 460 ed->purb = urb;
461
3e326ece
MK		 462 if (size >= (N_URB_TD - 1)) {
463 err("need %d TDs, only have %d", size, N_URB_TD);
464 return -1;
465 }
3e326ece
MK		 466 purb_priv->pipe = pipe;
467
468 /* fill the private part of the URB */
469 purb_priv->length = size;
470 purb_priv->ed = ed;
471 purb_priv->actual_length = 0;
472
473 /* allocate the TDs */
474 /* note that td[0] was allocated in ep_add_ed */
475 for (i = 0; i < size; i++) {
476 purb_priv->td[i] = td_alloc (dev);
477 if (!purb_priv->td[i]) {
478 purb_priv->length = i;
479 urb_free_priv (purb_priv);
480 err("sohci_submit_job: ENOMEM");
481 return -1;
482 }
483 }
484
485 if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
486 urb_free_priv (purb_priv);
487 err("sohci_submit_job: EINVAL");
488 return -1;
489 }
490
491 /* link the ed into a chain if is not already */
492 if (ed->state != ED_OPER)
493 ep_link (ohci, ed);
494
495 /* fill the TDs and link it to the ed */
496 td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
497
498 return 0;
499}
500
4dae14ce
ZW		 501static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)
502{
503 struct ohci_regs *regs = hc->regs;
504
505 switch (usb_pipetype (urb->pipe)) {
506 case PIPE_INTERRUPT:
507 /* implicitly requeued */
508 if (urb->dev->irq_handle &&
509 (urb->dev->irq_act_len = urb->actual_length)) {
510 writel (OHCI_INTR_WDH, &regs->intrenable);
511 readl (&regs->intrenable); /* PCI posting flush */
512 urb->dev->irq_handle(urb->dev);
513 writel (OHCI_INTR_WDH, &regs->intrdisable);
514 readl (&regs->intrdisable); /* PCI posting flush */
515 }
516 urb->actual_length = 0;
517 td_submit_job (
518 urb->dev,
519 urb->pipe,
520 urb->transfer_buffer,
521 urb->transfer_buffer_length,
522 NULL,
523 urb,
524 urb->interval);
525 break;
526 case PIPE_CONTROL:
527 case PIPE_BULK:
528 break;
529 default:
530 return 0;
531 }
532 return 1;
533}
534
3e326ece
MK		 535/*-------------------------------------------------------------------------*/
536
537#ifdef DEBUG
538/* tell us the current USB frame number */
539
540static int sohci_get_current_frame_number (struct usb_device *usb_dev)
541{
542 ohci_t *ohci = &gohci;
543
544 return m16_swap (ohci->hcca->frame_no);
545}
546#endif
547
4dae14ce
ZW		 548/*-------------------------------------------------------------------------*
549 * ED handling functions
550 *-------------------------------------------------------------------------*/
551
552/* search for the right branch to insert an interrupt ed into the int tree
553 * do some load ballancing;
554 * returns the branch and
555 * sets the interval to interval = 2^integer (ld (interval)) */
556
557static int ep_int_ballance (ohci_t * ohci, int interval, int load)
558{
559 int i, branch = 0;
560
561 /* search for the least loaded interrupt endpoint
562 * branch of all 32 branches
563 */
564 for (i = 0; i < 32; i++)
565 if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
566 branch = i;
567
568 branch = branch % interval;
569 for (i = branch; i < 32; i += interval)
570 ohci->ohci_int_load [i] += load;
571
572 return branch;
573}
574
575/*-------------------------------------------------------------------------*/
576
577/* 2^int( ld (inter)) */
578
579static int ep_2_n_interval (int inter)
580{
581 int i;
582 for (i = 0; ((inter >> i) > 1 ) && (i < 5); i++);
583 return 1 << i;
584}
585
586/*-------------------------------------------------------------------------*/
587
588/* the int tree is a binary tree
589 * in order to process it sequentially the indexes of the branches have to be mapped
590 * the mapping reverses the bits of a word of num_bits length */
591
592static int ep_rev (int num_bits, int word)
593{
594 int i, wout = 0;
595
596 for (i = 0; i < num_bits; i++)
597 wout |= (((word >> i) & 1) << (num_bits - i - 1));
598 return wout;
599}
600
3e326ece
MK		 601/*-------------------------------------------------------------------------*
602 * ED handling functions
603 *-------------------------------------------------------------------------*/
604
605/* link an ed into one of the HC chains */
606
607static int ep_link (ohci_t *ohci, ed_t *edi)
608{
609 volatile ed_t *ed = edi;
4dae14ce
ZW		 610 int int_branch;
611 int i;
612 int inter;
613 int interval;
614 int load;
615 __u32 * ed_p;
3e326ece
MK		 616
617 ed->state = ED_OPER;
4dae14ce 618 ed->int_interval = 0;
3e326ece
MK		 619
620 switch (ed->type) {
621 case PIPE_CONTROL:
622 ed->hwNextED = 0;
623 if (ohci->ed_controltail == NULL) {
624 writel (ed, &ohci->regs->ed_controlhead);
625 } else {
ae3b770e 626 ohci->ed_controltail->hwNextED = m32_swap ((unsigned long)ed);
3e326ece
MK		 627 }
628 ed->ed_prev = ohci->ed_controltail;
629 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
630 !ohci->ed_rm_list[1] && !ohci->sleeping) {
631 ohci->hc_control |= OHCI_CTRL_CLE;
632 writel (ohci->hc_control, &ohci->regs->control);
633 }
634 ohci->ed_controltail = edi;
635 break;
636
637 case PIPE_BULK:
638 ed->hwNextED = 0;
639 if (ohci->ed_bulktail == NULL) {
640 writel (ed, &ohci->regs->ed_bulkhead);
641 } else {
ae3b770e 642 ohci->ed_bulktail->hwNextED = m32_swap ((unsigned long)ed);
3e326ece
MK		 643 }
644 ed->ed_prev = ohci->ed_bulktail;
645 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
646 !ohci->ed_rm_list[1] && !ohci->sleeping) {
647 ohci->hc_control |= OHCI_CTRL_BLE;
648 writel (ohci->hc_control, &ohci->regs->control);
649 }
650 ohci->ed_bulktail = edi;
651 break;
4dae14ce
ZW		 652
653 case PIPE_INTERRUPT:
654 load = ed->int_load;
655 interval = ep_2_n_interval (ed->int_period);
656 ed->int_interval = interval;
657 int_branch = ep_int_ballance (ohci, interval, load);
658 ed->int_branch = int_branch;
659
660 for (i = 0; i < ep_rev (6, interval); i += inter) {
661 inter = 1;
662 for (ed_p = &(ohci->hcca->int_table[ep_rev (5, i) + int_branch]);
663 (*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval);
664 ed_p = &(((ed_t *)ed_p)->hwNextED))
665 inter = ep_rev (6, ((ed_t *)ed_p)->int_interval);
666 ed->hwNextED = *ed_p;
4a8527ef 667 *ed_p = m32_swap((unsigned long)ed);
4dae14ce
ZW		 668 }
669 break;
3e326ece
MK		 670 }
671 return 0;
672}
673
674/*-------------------------------------------------------------------------*/
675
4dae14ce
ZW		 676/* scan the periodic table to find and unlink this ED */
677static void periodic_unlink ( struct ohci *ohci, volatile struct ed *ed,
678 unsigned index, unsigned period)
679{
680 for (; index < NUM_INTS; index += period) {
681 __u32 *ed_p = &ohci->hcca->int_table [index];
682
683 /* ED might have been unlinked through another path */
684 while (*ed_p != 0) {
4a8527ef 685 if (((struct ed *)m32_swap ((unsigned long)ed_p)) == ed) {
4dae14ce
ZW		 686 *ed_p = ed->hwNextED;
687 break;
688 }
4a8527ef 689 ed_p = & (((struct ed *)m32_swap ((unsigned long)ed_p))->hwNextED);
4dae14ce
ZW		 690 }
691 }
692}
693
3e326ece
MK		 694/* unlink an ed from one of the HC chains.
695 * just the link to the ed is unlinked.
696 * the link from the ed still points to another operational ed or 0
697 * so the HC can eventually finish the processing of the unlinked ed */
698
53e336e9 699static int ep_unlink (ohci_t *ohci, ed_t *edi)
3e326ece 700{
53e336e9 701 volatile ed_t *ed = edi;
4dae14ce 702 int i;
53e336e9 703
3e326ece
MK		 704 ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
705
706 switch (ed->type) {
707 case PIPE_CONTROL:
708 if (ed->ed_prev == NULL) {
709 if (!ed->hwNextED) {
710 ohci->hc_control &= ~OHCI_CTRL_CLE;
711 writel (ohci->hc_control, &ohci->regs->control);
712 }
713 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
714 } else {
715 ed->ed_prev->hwNextED = ed->hwNextED;
716 }
717 if (ohci->ed_controltail == ed) {
718 ohci->ed_controltail = ed->ed_prev;
719 } else {
720 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
721 }
722 break;
723
724 case PIPE_BULK:
725 if (ed->ed_prev == NULL) {
726 if (!ed->hwNextED) {
727 ohci->hc_control &= ~OHCI_CTRL_BLE;
728 writel (ohci->hc_control, &ohci->regs->control);
729 }
730 writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
731 } else {
732 ed->ed_prev->hwNextED = ed->hwNextED;
733 }
734 if (ohci->ed_bulktail == ed) {
735 ohci->ed_bulktail = ed->ed_prev;
736 } else {
737 ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
738 }
739 break;
4dae14ce
ZW		 740
741 case PIPE_INTERRUPT:
742 periodic_unlink (ohci, ed, 0, 1);
743 for (i = ed->int_branch; i < 32; i += ed->int_interval)
744 ohci->ohci_int_load[i] -= ed->int_load;
745 break;
3e326ece
MK		 746 }
747 ed->state = ED_UNLINK;
748 return 0;
749}
750
3e326ece
MK		 751/*-------------------------------------------------------------------------*/
752
ddf83a2f
MK		 753/* add/reinit an endpoint; this should be done once at the
754 * usb_set_configuration command, but the USB stack is a little bit
755 * stateless so we do it at every transaction if the state of the ed
756 * is ED_NEW then a dummy td is added and the state is changed to
757 * ED_UNLINK in all other cases the state is left unchanged the ed
758 * info fields are setted anyway even though most of them should not
759 * change
760 */
4dae14ce
ZW		 761static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe,
762 int interval, int load)
3e326ece
MK		 763{
764 td_t *td;
765 ed_t *ed_ret;
766 volatile ed_t *ed;
767
768 ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
769 (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
770
771 if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
772 err("ep_add_ed: pending delete");
773 /* pending delete request */
774 return NULL;
775 }
776
777 if (ed->state == ED_NEW) {
778 ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
779 /* dummy td; end of td list for ed */
780 td = td_alloc (usb_dev);
ae3b770e 781 ed->hwTailP = m32_swap ((unsigned long)td);
3e326ece
MK		 782 ed->hwHeadP = ed->hwTailP;
783 ed->state = ED_UNLINK;
784 ed->type = usb_pipetype (pipe);
785 ohci_dev.ed_cnt++;
786 }
787
788 ed->hwINFO = m32_swap (usb_pipedevice (pipe)
789 | usb_pipeendpoint (pipe) << 7
790 | (usb_pipeisoc (pipe)? 0x8000: 0)
791 | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
792 | usb_pipeslow (pipe) << 13
793 | usb_maxpacket (usb_dev, pipe) << 16);
794
4dae14ce
ZW		 795 if (ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK) {
796 ed->int_period = interval;
797 ed->int_load = load;
798 }
799
3e326ece
MK		 800 return ed_ret;
801}
802
803/*-------------------------------------------------------------------------*
804 * TD handling functions
805 *-------------------------------------------------------------------------*/
806
807/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
808
809static void td_fill (ohci_t *ohci, unsigned int info,
810 void *data, int len,
811 struct usb_device *dev, int index, urb_priv_t *urb_priv)
812{
813 volatile td_t *td, *td_pt;
814#ifdef OHCI_FILL_TRACE
815 int i;
816#endif
817
818 if (index > urb_priv->length) {
819 err("index > length");
820 return;
821 }
822 /* use this td as the next dummy */
823 td_pt = urb_priv->td [index];
824 td_pt->hwNextTD = 0;
825
826 /* fill the old dummy TD */
827 td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
828
829 td->ed = urb_priv->ed;
830 td->next_dl_td = NULL;
831 td->index = index;
832 td->data = (__u32)data;
833#ifdef OHCI_FILL_TRACE
834 if ((usb_pipetype(urb_priv->pipe) == PIPE_BULK) && usb_pipeout(urb_priv->pipe)) {
835 for (i = 0; i < len; i++)
836 printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
837 printf("\n");
838 }
839#endif
840 if (!len)
841 data = 0;
842
843 td->hwINFO = m32_swap (info);
ae3b770e 844 td->hwCBP = m32_swap ((unsigned long)data);
3e326ece 845 if (data)
ae3b770e 846 td->hwBE = m32_swap ((unsigned long)(data + len - 1));
3e326ece
MK		 847 else
848 td->hwBE = 0;
ae3b770e 849 td->hwNextTD = m32_swap ((unsigned long)td_pt);
3e326ece
MK		 850
851 /* append to queue */
852 td->ed->hwTailP = td->hwNextTD;
853}
854
855/*-------------------------------------------------------------------------*/
856
857/* prepare all TDs of a transfer */
858
859static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
860 int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
861{
862 ohci_t *ohci = &gohci;
863 int data_len = transfer_len;
864 void *data;
865 int cnt = 0;
866 __u32 info = 0;
867 unsigned int toggle = 0;
868
869 /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
870 if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
871 toggle = TD_T_TOGGLE;
872 } else {
873 toggle = TD_T_DATA0;
874 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
875 }
876 urb->td_cnt = 0;
877 if (data_len)
878 data = buffer;
879 else
880 data = 0;
881
882 switch (usb_pipetype (pipe)) {
883 case PIPE_BULK:
884 info = usb_pipeout (pipe)?
885 TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
886 while(data_len > 4096) {
887 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
888 data += 4096; data_len -= 4096; cnt++;
889 }
890 info = usb_pipeout (pipe)?
891 TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
892 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
893 cnt++;
894
895 if (!ohci->sleeping)
896 writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
897 break;
898
899 case PIPE_CONTROL:
900 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
901 td_fill (ohci, info, setup, 8, dev, cnt++, urb);
902 if (data_len > 0) {
903 info = usb_pipeout (pipe)?
904 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
905 /* NOTE: mishandles transfers >8K, some >4K */
906 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
907 }
908 info = usb_pipeout (pipe)?
909 TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
910 td_fill (ohci, info, data, 0, dev, cnt++, urb);
911 if (!ohci->sleeping)
912 writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
913 break;
4dae14ce
ZW		 914
915 case PIPE_INTERRUPT:
916 info = usb_pipeout (urb->pipe)?
917 TD_CC | TD_DP_OUT | toggle:
918 TD_CC | TD_R | TD_DP_IN | toggle;
919 td_fill (ohci, info, data, data_len, dev, cnt++, urb);
920 break;
3e326ece
MK		 921 }
922 if (urb->length != cnt)
923 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
924}
925
926/*-------------------------------------------------------------------------*
927 * Done List handling functions
928 *-------------------------------------------------------------------------*/
929
3e326ece
MK		 930/* calculate the transfer length and update the urb */
931
932static void dl_transfer_length(td_t * td)
933{
934 __u32 tdINFO, tdBE, tdCBP;
4dae14ce 935 urb_priv_t *lurb_priv = td->ed->purb;
3e326ece
MK		 936
937 tdINFO = m32_swap (td->hwINFO);
938 tdBE = m32_swap (td->hwBE);
939 tdCBP = m32_swap (td->hwCBP);
940
3e326ece
MK		 941 if (!(usb_pipetype (lurb_priv->pipe) == PIPE_CONTROL &&
942 ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
943 if (tdBE != 0) {
944 if (td->hwCBP == 0)
945 lurb_priv->actual_length += tdBE - td->data + 1;
946 else
947 lurb_priv->actual_length += tdCBP - td->data;
948 }
949 }
950}
951
952/*-------------------------------------------------------------------------*/
953
954/* replies to the request have to be on a FIFO basis so
955 * we reverse the reversed done-list */
956
957static td_t * dl_reverse_done_list (ohci_t *ohci)
958{
959 __u32 td_list_hc;
960 td_t *td_rev = NULL;
961 td_t *td_list = NULL;
962 urb_priv_t *lurb_priv = NULL;
963
964 td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
965 ohci->hcca->done_head = 0;
966
967 while (td_list_hc) {
968 td_list = (td_t *)td_list_hc;
969
970 if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
4dae14ce 971 lurb_priv = td_list->ed->purb;
3e326ece
MK		 972 dbg(" USB-error/status: %x : %p",
973 TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
974 if (td_list->ed->hwHeadP & m32_swap (0x1)) {
975 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
976 td_list->ed->hwHeadP =
977 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
978 (td_list->ed->hwHeadP & m32_swap (0x2));
979 lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
980 } else
981 td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
982 }
53e336e9
MK		 983#ifdef CONFIG_MPC5200
984 td_list->hwNextTD = 0;
985#endif
3e326ece
MK		 986 }
987
988 td_list->next_dl_td = td_rev;
989 td_rev = td_list;
990 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
991 }
992 return td_list;
993}
994
995/*-------------------------------------------------------------------------*/
996
997/* td done list */
998static int dl_done_list (ohci_t *ohci, td_t *td_list)
999{
1000 td_t *td_list_next = NULL;
1001 ed_t *ed;
1002 int cc = 0;
1003 int stat = 0;
1004 /* urb_t *urb; */
1005 urb_priv_t *lurb_priv;
1006 __u32 tdINFO, edHeadP, edTailP;
1007
1008 while (td_list) {
1009 td_list_next = td_list->next_dl_td;
1010
3e326ece
MK		 1011 tdINFO = m32_swap (td_list->hwINFO);
1012
1013 ed = td_list->ed;
4dae14ce 1014 lurb_priv = ed->purb;
3e326ece
MK		 1015
1016 dl_transfer_length(td_list);
1017
1018 /* error code of transfer */
1019 cc = TD_CC_GET (tdINFO);
1020 if (cc != 0) {
1021 dbg("ConditionCode %#x", cc);
1022 stat = cc_to_error[cc];
1023 }
ae79f606 1024
ddf83a2f
MK		 1025 /* see if this done list makes for all TD's of current URB,
1026 * and mark the URB finished if so */
1027 if (++(lurb_priv->td_cnt) == lurb_priv->length) {
ae3b770e
MK		 1028#if 1
1029 if ((ed->state & (ED_OPER | ED_UNLINK)) &&
1030 (lurb_priv->state != URB_DEL))
1031#else
ddf83a2f 1032 if ((ed->state & (ED_OPER | ED_UNLINK)))
4dae14ce
ZW		 1033#endif
1034 lurb_priv->finished = sohci_return_job(ohci,
1035 lurb_priv);
ddf83a2f
MK		 1036 else
1037 dbg("dl_done_list: strange.., ED state %x, ed->state\n");
1038 } else
1039 dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
1040 lurb_priv->length);
4dae14ce
ZW		 1041 if (ed->state != ED_NEW &&
1042 (usb_pipetype (lurb_priv->pipe) != PIPE_INTERRUPT)) {
3e326ece
MK		 1043 edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
1044 edTailP = m32_swap (ed->hwTailP);
1045
1046 /* unlink eds if they are not busy */
1047 if ((edHeadP == edTailP) && (ed->state == ED_OPER))
1048 ep_unlink (ohci, ed);
1049 }
1050
1051 td_list = td_list_next;
1052 }
1053 return stat;
1054}
1055
1056/*-------------------------------------------------------------------------*
1057 * Virtual Root Hub
1058 *-------------------------------------------------------------------------*/
1059
1060/* Device descriptor */
1061static __u8 root_hub_dev_des[] =
1062{
1063 0x12, /* __u8 bLength; */
1064 0x01, /* __u8 bDescriptorType; Device */
1065 0x10, /* __u16 bcdUSB; v1.1 */
1066 0x01,
1067 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
1068 0x00, /* __u8 bDeviceSubClass; */
1069 0x00, /* __u8 bDeviceProtocol; */
1070 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
1071 0x00, /* __u16 idVendor; */
1072 0x00,
1073 0x00, /* __u16 idProduct; */
1074 0x00,
1075 0x00, /* __u16 bcdDevice; */
1076 0x00,
1077 0x00, /* __u8 iManufacturer; */
1078 0x01, /* __u8 iProduct; */
1079 0x00, /* __u8 iSerialNumber; */
1080 0x01 /* __u8 bNumConfigurations; */
1081};
1082
3e326ece
MK		 1083/* Configuration descriptor */
1084static __u8 root_hub_config_des[] =
1085{
1086 0x09, /* __u8 bLength; */
1087 0x02, /* __u8 bDescriptorType; Configuration */
1088 0x19, /* __u16 wTotalLength; */
1089 0x00,
1090 0x01, /* __u8 bNumInterfaces; */
1091 0x01, /* __u8 bConfigurationValue; */
1092 0x00, /* __u8 iConfiguration; */
1093 0x40, /* __u8 bmAttributes;
1094 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
1095 0x00, /* __u8 MaxPower; */
1096
1097 /* interface */
1098 0x09, /* __u8 if_bLength; */
1099 0x04, /* __u8 if_bDescriptorType; Interface */
1100 0x00, /* __u8 if_bInterfaceNumber; */
1101 0x00, /* __u8 if_bAlternateSetting; */
1102 0x01, /* __u8 if_bNumEndpoints; */
1103 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
1104 0x00, /* __u8 if_bInterfaceSubClass; */
1105 0x00, /* __u8 if_bInterfaceProtocol; */
1106 0x00, /* __u8 if_iInterface; */
1107
1108 /* endpoint */
1109 0x07, /* __u8 ep_bLength; */
1110 0x05, /* __u8 ep_bDescriptorType; Endpoint */
1111 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
1112 0x03, /* __u8 ep_bmAttributes; Interrupt */
1113 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
1114 0x00,
1115 0xff /* __u8 ep_bInterval; 255 ms */
1116};
1117
1118static unsigned char root_hub_str_index0[] =
1119{
1120 0x04, /* __u8 bLength; */
1121 0x03, /* __u8 bDescriptorType; String-descriptor */
1122 0x09, /* __u8 lang ID */
1123 0x04, /* __u8 lang ID */
1124};
1125
1126static unsigned char root_hub_str_index1[] =
1127{
1128 28, /* __u8 bLength; */
1129 0x03, /* __u8 bDescriptorType; String-descriptor */
1130 'O', /* __u8 Unicode */
1131 0, /* __u8 Unicode */
1132 'H', /* __u8 Unicode */
1133 0, /* __u8 Unicode */
1134 'C', /* __u8 Unicode */
1135 0, /* __u8 Unicode */
1136 'I', /* __u8 Unicode */
1137 0, /* __u8 Unicode */
1138 ' ', /* __u8 Unicode */
1139 0, /* __u8 Unicode */
1140 'R', /* __u8 Unicode */
1141 0, /* __u8 Unicode */
1142 'o', /* __u8 Unicode */
1143 0, /* __u8 Unicode */
1144 'o', /* __u8 Unicode */
1145 0, /* __u8 Unicode */
1146 't', /* __u8 Unicode */
1147 0, /* __u8 Unicode */
1148 ' ', /* __u8 Unicode */
1149 0, /* __u8 Unicode */
1150 'H', /* __u8 Unicode */
1151 0, /* __u8 Unicode */
1152 'u', /* __u8 Unicode */
1153 0, /* __u8 Unicode */
1154 'b', /* __u8 Unicode */
1155 0, /* __u8 Unicode */
1156};
1157
1158/* Hub class-specific descriptor is constructed dynamically */
1159
3e326ece
MK		 1160/*-------------------------------------------------------------------------*/
1161
1162#define OK(x) len = (x); break
1163#ifdef DEBUG
1164#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
1165#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
1166#else
1167#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
1168#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
1169#endif
1170#define RD_RH_STAT roothub_status(&gohci)
1171#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
1172
1173/* request to virtual root hub */
1174
1175int rh_check_port_status(ohci_t *controller)
1176{
1177 __u32 temp, ndp, i;
1178 int res;
1179
1180 res = -1;
1181 temp = roothub_a (controller);
1182 ndp = (temp & RH_A_NDP);
1183#ifdef CONFIG_AT91C_PQFP_UHPBUG
1184 ndp = (ndp == 2) ? 1:0;
1185#endif
1186 for (i = 0; i < ndp; i++) {
1187 temp = roothub_portstatus (controller, i);
1188 /* check for a device disconnect */
1189 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
1190 (RH_PS_PESC | RH_PS_CSC)) &&
1191 ((temp & RH_PS_CCS) == 0)) {
1192 res = i;
1193 break;
1194 }
1195 }
1196 return res;
1197}
1198
1199static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
1200 void *buffer, int transfer_len, struct devrequest *cmd)
1201{
1202 void * data = buffer;
1203 int leni = transfer_len;
1204 int len = 0;
1205 int stat = 0;
1206 __u32 datab[4];
1207 __u8 *data_buf = (__u8 *)datab;
1208 __u16 bmRType_bReq;
1209 __u16 wValue;
1210 __u16 wIndex;
1211 __u16 wLength;
1212
1213#ifdef DEBUG
4dae14ce 1214pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
3e326ece
MK		 1215#else
1216 wait_ms(1);
1217#endif
1218 if ((pipe & PIPE_INTERRUPT) == PIPE_INTERRUPT) {
1219 info("Root-Hub submit IRQ: NOT implemented");
1220 return 0;
1221 }
1222
1223 bmRType_bReq = cmd->requesttype | (cmd->request << 8);
fb63939b
CE		 1224 wValue = le16_to_cpu (cmd->value);
1225 wIndex = le16_to_cpu (cmd->index);
1226 wLength = le16_to_cpu (cmd->length);
3e326ece
MK		 1227
1228 info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
1229 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
1230
1231 switch (bmRType_bReq) {
1232 /* Request Destination:
1233 without flags: Device,
1234 RH_INTERFACE: interface,
1235 RH_ENDPOINT: endpoint,
1236 RH_CLASS means HUB here,
1237 RH_OTHER | RH_CLASS almost ever means HUB_PORT here
1238 */
1239
1240 case RH_GET_STATUS:
fc43be47 1241 *(__u16 *) data_buf = cpu_to_le16 (1); OK (2);
3e326ece 1242 case RH_GET_STATUS | RH_INTERFACE:
fc43be47 1243 *(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
3e326ece 1244 case RH_GET_STATUS | RH_ENDPOINT:
fc43be47 1245 *(__u16 *) data_buf = cpu_to_le16 (0); OK (2);
3e326ece 1246 case RH_GET_STATUS | RH_CLASS:
fc43be47 1247 *(__u32 *) data_buf = cpu_to_le32 (
3e326ece
MK		 1248 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
1249 OK (4);
1250 case RH_GET_STATUS | RH_OTHER | RH_CLASS:
fc43be47 1251 *(__u32 *) data_buf = cpu_to_le32 (RD_RH_PORTSTAT); OK (4);
3e326ece
MK		 1252
1253 case RH_CLEAR_FEATURE | RH_ENDPOINT:
1254 switch (wValue) {
1255 case (RH_ENDPOINT_STALL): OK (0);
1256 }
1257 break;
1258
1259 case RH_CLEAR_FEATURE | RH_CLASS:
1260 switch (wValue) {
1261 case RH_C_HUB_LOCAL_POWER:
1262 OK(0);
1263 case (RH_C_HUB_OVER_CURRENT):
1264 WR_RH_STAT(RH_HS_OCIC); OK (0);
1265 }
1266 break;
1267
1268 case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
1269 switch (wValue) {
1270 case (RH_PORT_ENABLE):
1271 WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
1272 case (RH_PORT_SUSPEND):
1273 WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
1274 case (RH_PORT_POWER):
1275 WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
1276 case (RH_C_PORT_CONNECTION):
1277 WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
1278 case (RH_C_PORT_ENABLE):
1279 WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
1280 case (RH_C_PORT_SUSPEND):
1281 WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
1282 case (RH_C_PORT_OVER_CURRENT):
1283 WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
1284 case (RH_C_PORT_RESET):
1285 WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
1286 }
1287 break;
1288
1289 case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
1290 switch (wValue) {
1291 case (RH_PORT_SUSPEND):
1292 WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
1293 case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
1294 if (RD_RH_PORTSTAT & RH_PS_CCS)
1295 WR_RH_PORTSTAT (RH_PS_PRS);
1296 OK (0);
1297 case (RH_PORT_POWER):
d98c0885
RG		 1298 WR_RH_PORTSTAT (RH_PS_PPS );
1299 wait_ms(100);
1300 OK (0);
3e326ece
MK		 1301 case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
1302 if (RD_RH_PORTSTAT & RH_PS_CCS)
1303 WR_RH_PORTSTAT (RH_PS_PES );
1304 OK (0);
1305 }
1306 break;
1307
1308 case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
1309
1310 case RH_GET_DESCRIPTOR:
1311 switch ((wValue & 0xff00) >> 8) {
1312 case (0x01): /* device descriptor */
1313 len = min_t(unsigned int,
1314 leni,
1315 min_t(unsigned int,
1316 sizeof (root_hub_dev_des),
1317 wLength));
1318 data_buf = root_hub_dev_des; OK(len);
1319 case (0x02): /* configuration descriptor */
1320 len = min_t(unsigned int,
1321 leni,
1322 min_t(unsigned int,
1323 sizeof (root_hub_config_des),
1324 wLength));
1325 data_buf = root_hub_config_des; OK(len);
1326 case (0x03): /* string descriptors */
1327 if(wValue==0x0300) {
1328 len = min_t(unsigned int,
1329 leni,
1330 min_t(unsigned int,
1331 sizeof (root_hub_str_index0),
1332 wLength));
1333 data_buf = root_hub_str_index0;
1334 OK(len);
1335 }
1336 if(wValue==0x0301) {
1337 len = min_t(unsigned int,
1338 leni,
1339 min_t(unsigned int,
1340 sizeof (root_hub_str_index1),
1341 wLength));
1342 data_buf = root_hub_str_index1;
1343 OK(len);
1344 }
1345 default:
1346 stat = USB_ST_STALLED;
1347 }
1348 break;
1349
1350 case RH_GET_DESCRIPTOR | RH_CLASS:
1351 {
1352 __u32 temp = roothub_a (&gohci);
1353
1354 data_buf [0] = 9; /* min length; */
1355 data_buf [1] = 0x29;
1356 data_buf [2] = temp & RH_A_NDP;
1357#ifdef CONFIG_AT91C_PQFP_UHPBUG
1358 data_buf [2] = (data_buf [2] == 2) ? 1:0;
1359#endif
3e326ece
MK		 1360 data_buf [3] = 0;
1361 if (temp & RH_A_PSM) /* per-port power switching? */
1362 data_buf [3] |= 0x1;
1363 if (temp & RH_A_NOCP) /* no overcurrent reporting? */
1364 data_buf [3] |= 0x10;
3e326ece
MK		 1365 else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
1366 data_buf [3] |= 0x8;
3e326ece
MK		 1367
1368 /* corresponds to data_buf[4-7] */
1369 datab [1] = 0;
1370 data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1371 temp = roothub_b (&gohci);
1372 data_buf [7] = temp & RH_B_DR;
1373 if (data_buf [2] < 7) {
1374 data_buf [8] = 0xff;
1375 } else {
1376 data_buf [0] += 2;
1377 data_buf [8] = (temp & RH_B_DR) >> 8;
1378 data_buf [10] = data_buf [9] = 0xff;
1379 }
1380
1381 len = min_t(unsigned int, leni,
ddf83a2f 1382 min_t(unsigned int, data_buf [0], wLength));
3e326ece
MK		 1383 OK (len);
1384 }
1385
1386 case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
1387
1388 case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
1389
1390 default:
1391 dbg ("unsupported root hub command");
1392 stat = USB_ST_STALLED;
1393 }
1394
1395#ifdef DEBUG
1396 ohci_dump_roothub (&gohci, 1);
1397#else
1398 wait_ms(1);
1399#endif
1400
1401 len = min_t(int, len, leni);
1402 if (data != data_buf)
1403 memcpy (data, data_buf, len);
1404 dev->act_len = len;
1405 dev->status = stat;
1406
1407#ifdef DEBUG
4dae14ce 1408 pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
3e326ece
MK		 1409#else
1410 wait_ms(1);
1411#endif
1412
1413 return stat;
1414}
1415
1416/*-------------------------------------------------------------------------*/
1417
1418/* common code for handling submit messages - used for all but root hub */
1419/* accesses. */
1420int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1421 int transfer_len, struct devrequest *setup, int interval)
1422{
1423 int stat = 0;
1424 int maxsize = usb_maxpacket(dev, pipe);
1425 int timeout;
4dae14ce
ZW		 1426 urb_priv_t *urb;
1427
1428 urb = malloc(sizeof(urb_priv_t));
1429 memset(urb, 0, sizeof(urb_priv_t));
1430
1431 urb->dev = dev;
1432 urb->pipe = pipe;
1433 urb->transfer_buffer = buffer;
1434 urb->transfer_buffer_length = transfer_len;
1435 urb->interval = interval;
3e326ece
MK		 1436
1437 /* device pulled? Shortcut the action. */
1438 if (devgone == dev) {
1439 dev->status = USB_ST_CRC_ERR;
1440 return 0;
1441 }
1442
1443#ifdef DEBUG
4dae14ce
ZW		 1444 urb->actual_length = 0;
1445 pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
3e326ece
MK		 1446#else
1447 wait_ms(1);
1448#endif
1449 if (!maxsize) {
1450 err("submit_common_message: pipesize for pipe %lx is zero",
1451 pipe);
1452 return -1;
1453 }
1454
4dae14ce 1455 if (sohci_submit_job(urb, setup) < 0) {
3e326ece
MK		 1456 err("sohci_submit_job failed");
1457 return -1;
1458 }
1459
ae3b770e 1460#if 0
3e326ece
MK		 1461 wait_ms(10);
1462 /* ohci_dump_status(&gohci); */
ae3b770e 1463#endif
3e326ece
MK		 1464
1465 /* allow more time for a BULK device to react - some are slow */
1466#define BULK_TO 5000 /* timeout in milliseconds */
1467 if (usb_pipetype (pipe) == PIPE_BULK)
1468 timeout = BULK_TO;
1469 else
1470 timeout = 100;
1471
1472 /* wait for it to complete */
1473 for (;;) {
1474 /* check whether the controller is done */
1475 stat = hc_interrupt();
1476 if (stat < 0) {
1477 stat = USB_ST_CRC_ERR;
1478 break;
1479 }
ddf83a2f 1480
ddf83a2f
MK		 1481 /* NOTE: since we are not interrupt driven in U-Boot and always
1482 * handle only one URB at a time, we cannot assume the
1483 * transaction finished on the first successful return from
1484 * hc_interrupt().. unless the flag for current URB is set,
1485 * meaning that all TD's to/from device got actually
1486 * transferred and processed. If the current URB is not
1487 * finished we need to re-iterate this loop so as
1488 * hc_interrupt() gets called again as there needs to be some
1489 * more TD's to process still */
4dae14ce 1490 if ((stat >= 0) && (stat != 0xff) && (urb->finished)) {
3e326ece
MK		 1491 /* 0xff is returned for an SF-interrupt */
1492 break;
1493 }
ddf83a2f 1494
3e326ece
MK		 1495 if (--timeout) {
1496 wait_ms(1);
4dae14ce
ZW		 1497 if (!urb->finished)
1498 dbg("\%");
1499
3e326ece
MK		 1500 } else {
1501 err("CTL:TIMEOUT ");
ddf83a2f 1502 dbg("submit_common_msg: TO status %x\n", stat);
4dae14ce 1503 urb->finished = 1;
3e326ece
MK		 1504 stat = USB_ST_CRC_ERR;
1505 break;
1506 }
1507 }
3e326ece
MK		 1508
1509 dev->status = stat;
1510 dev->act_len = transfer_len;
1511
1512#ifdef DEBUG
4dae14ce 1513 pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
3e326ece
MK		 1514#else
1515 wait_ms(1);
1516#endif
1517
1518 /* free TDs in urb_priv */
4dae14ce
ZW		 1519 if (usb_pipetype (pipe) != PIPE_INTERRUPT)
1520 urb_free_priv (urb);
3e326ece
MK		 1521 return 0;
1522}
1523
1524/* submit routines called from usb.c */
1525int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1526 int transfer_len)
1527{
1528 info("submit_bulk_msg");
1529 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1530}
1531
1532int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1533 int transfer_len, struct devrequest *setup)
1534{
1535 int maxsize = usb_maxpacket(dev, pipe);
1536
1537 info("submit_control_msg");
1538#ifdef DEBUG
4dae14ce 1539 pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
3e326ece
MK		 1540#else
1541 wait_ms(1);
1542#endif
1543 if (!maxsize) {
1544 err("submit_control_message: pipesize for pipe %lx is zero",
1545 pipe);
1546 return -1;
1547 }
1548 if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1549 gohci.rh.dev = dev;
1550 /* root hub - redirect */
1551 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1552 setup);
1553 }
1554
1555 return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1556}
1557
1558int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1559 int transfer_len, int interval)
1560{
1561 info("submit_int_msg");
4dae14ce
ZW		 1562 return submit_common_msg(dev, pipe, buffer, transfer_len, NULL,
1563 interval);
3e326ece
MK		 1564}
1565
1566/*-------------------------------------------------------------------------*
1567 * HC functions
1568 *-------------------------------------------------------------------------*/
1569
1570/* reset the HC and BUS */
1571
1572static int hc_reset (ohci_t *ohci)
1573{
1574 int timeout = 30;
1575 int smm_timeout = 50; /* 0,5 sec */
1576
1577 dbg("%s\n", __FUNCTION__);
1578
1579 if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1580 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1581 info("USB HC TakeOver from SMM");
1582 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1583 wait_ms (10);
1584 if (--smm_timeout == 0) {
1585 err("USB HC TakeOver failed!");
1586 return -1;
1587 }
1588 }
1589 }
1590
1591 /* Disable HC interrupts */
1592 writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1593
1594 dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;\n",
1595 ohci->slot_name,
1596 readl(&ohci->regs->control));
1597
1598 /* Reset USB (needed by some controllers) */
53e336e9
MK		 1599 ohci->hc_control = 0;
1600 writel (ohci->hc_control, &ohci->regs->control);
3e326ece
MK		 1601
1602 /* HC Reset requires max 10 us delay */
1603 writel (OHCI_HCR, &ohci->regs->cmdstatus);
1604 while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1605 if (--timeout == 0) {
1606 err("USB HC reset timed out!");
1607 return -1;
1608 }
1609 udelay (1);
1610 }
1611 return 0;
1612}
1613
1614/*-------------------------------------------------------------------------*/
1615
1616/* Start an OHCI controller, set the BUS operational
1617 * enable interrupts
1618 * connect the virtual root hub */
1619
1620static int hc_start (ohci_t * ohci)
1621{
1622 __u32 mask;
1623 unsigned int fminterval;
1624
1625 ohci->disabled = 1;
1626
1627 /* Tell the controller where the control and bulk lists are
1628 * The lists are empty now. */
1629
1630 writel (0, &ohci->regs->ed_controlhead);
1631 writel (0, &ohci->regs->ed_bulkhead);
1632
1633 writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1634
1635 fminterval = 0x2edf;
1636 writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1637 fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1638 writel (fminterval, &ohci->regs->fminterval);
1639 writel (0x628, &ohci->regs->lsthresh);
1640
1641 /* start controller operations */
1642 ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1643 ohci->disabled = 0;
1644 writel (ohci->hc_control, &ohci->regs->control);
1645
1646 /* disable all interrupts */
1647 mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1648 OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1649 OHCI_INTR_OC | OHCI_INTR_MIE);
1650 writel (mask, &ohci->regs->intrdisable);
1651 /* clear all interrupts */
1652 mask &= ~OHCI_INTR_MIE;
1653 writel (mask, &ohci->regs->intrstatus);
1654 /* Choose the interrupts we care about now - but w/o MIE */
1655 mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1656 writel (mask, &ohci->regs->intrenable);
1657
1658#ifdef OHCI_USE_NPS
1659 /* required for AMD-756 and some Mac platforms */
1660 writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1661 &ohci->regs->roothub.a);
1662 writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1663#endif /* OHCI_USE_NPS */
1664
1665#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
1666 /* POTPGT delay is bits 24-31, in 2 ms units. */
1667 mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1668
1669 /* connect the virtual root hub */
1670 ohci->rh.devnum = 0;
1671
1672 return 0;
1673}
1674
1675/*-------------------------------------------------------------------------*/
1676
4dae14ce
ZW		 1677/* Poll USB interrupt. */
1678void usb_event_poll(void)
1679{
1680 hc_interrupt();
1681}
1682
3e326ece
MK		 1683/* an interrupt happens */
1684
ddf83a2f 1685static int hc_interrupt (void)
3e326ece
MK		 1686{
1687 ohci_t *ohci = &gohci;
1688 struct ohci_regs *regs = ohci->regs;
1689 int ints;
1690 int stat = -1;
1691
ddf83a2f
MK		 1692 if ((ohci->hcca->done_head != 0) &&
1693 !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1694 ints = OHCI_INTR_WDH;
1695 } else if ((ints = readl (&regs->intrstatus)) == ~(u32)0) {
1696 ohci->disabled++;
1697 err ("%s device removed!", ohci->slot_name);
1698 return -1;
1699 } else if ((ints &= readl (&regs->intrenable)) == 0) {
1700 dbg("hc_interrupt: returning..\n");
1701 return 0xff;
1702 }
ae79f606 1703
3e326ece
MK		 1704 /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1705
1706 if (ints & OHCI_INTR_RHSC) {
1707 got_rhsc = 1;
ddf83a2f 1708 stat = 0xff;
3e326ece
MK		 1709 }
1710
1711 if (ints & OHCI_INTR_UE) {
1712 ohci->disabled++;
1713 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1714 ohci->slot_name);
1715 /* e.g. due to PCI Master/Target Abort */
1716
1717#ifdef DEBUG
1718 ohci_dump (ohci, 1);
1719#else
1720 wait_ms(1);
1721#endif
1722 /* FIXME: be optimistic, hope that bug won't repeat often. */
1723 /* Make some non-interrupt context restart the controller. */
1724 /* Count and limit the retries though; either hardware or */
1725 /* software errors can go forever... */
1726 hc_reset (ohci);
1727 return -1;
1728 }
1729
1730 if (ints & OHCI_INTR_WDH) {
1731 wait_ms(1);
1732 writel (OHCI_INTR_WDH, &regs->intrdisable);
4dae14ce 1733 (void)readl (&regs->intrdisable); /* flush */
3e326ece
MK		 1734 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1735 writel (OHCI_INTR_WDH, &regs->intrenable);
4dae14ce 1736 (void)readl (&regs->intrdisable); /* flush */
3e326ece
MK		 1737 }
1738
1739 if (ints & OHCI_INTR_SO) {
1740 dbg("USB Schedule overrun\n");
1741 writel (OHCI_INTR_SO, &regs->intrenable);
1742 stat = -1;
1743 }
1744
1745 /* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
1746 if (ints & OHCI_INTR_SF) {
1747 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1748 wait_ms(1);
1749 writel (OHCI_INTR_SF, &regs->intrdisable);
1750 if (ohci->ed_rm_list[frame] != NULL)
1751 writel (OHCI_INTR_SF, &regs->intrenable);
1752 stat = 0xff;
1753 }
1754
1755 writel (ints, &regs->intrstatus);
1756 return stat;
1757}
1758
1759/*-------------------------------------------------------------------------*/
1760
1761/*-------------------------------------------------------------------------*/
1762
1763/* De-allocate all resources.. */
1764
1765static void hc_release_ohci (ohci_t *ohci)
1766{
1767 dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1768
1769 if (!ohci->disabled)
1770 hc_reset (ohci);
1771}
1772
1773/*-------------------------------------------------------------------------*/
1774
1775/*
1776 * low level initalisation routine, called from usb.c
1777 */
1778static char ohci_inited = 0;
1779
1780int usb_lowlevel_init(void)
1781{
4dae14ce
ZW		 1782#ifdef CONFIG_PCI_OHCI
1783 pci_dev_t pdev;
1784#endif
24e37645 1785
ddf83a2f 1786#ifdef CFG_USB_OHCI_CPU_INIT
24e37645
MK		 1787 /* cpu dependant init */
1788 if(usb_cpu_init())
3e326ece 1789 return -1;
24e37645 1790#endif
3e326ece 1791
ddf83a2f 1792#ifdef CFG_USB_OHCI_BOARD_INIT
24e37645
MK		 1793 /* board dependant init */
1794 if(usb_board_init())
1795 return -1;
1796#endif
3e326ece 1797 memset (&gohci, 0, sizeof (ohci_t));
3e326ece
MK		 1798
1799 /* align the storage */
1800 if ((__u32)&ghcca[0] & 0xff) {
1801 err("HCCA not aligned!!");
1802 return -1;
1803 }
1804 phcca = &ghcca[0];
1805 info("aligned ghcca %p", phcca);
1806 memset(&ohci_dev, 0, sizeof(struct ohci_device));
1807 if ((__u32)&ohci_dev.ed[0] & 0x7) {
1808 err("EDs not aligned!!");
1809 return -1;
1810 }
1811 memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1812 if ((__u32)gtd & 0x7) {
1813 err("TDs not aligned!!");
1814 return -1;
1815 }
1816 ptd = gtd;
1817 gohci.hcca = phcca;
1818 memset (phcca, 0, sizeof (struct ohci_hcca));
1819
1820 gohci.disabled = 1;
1821 gohci.sleeping = 0;
1822 gohci.irq = -1;
4dae14ce 1823#ifdef CONFIG_PCI_OHCI
477434c6 1824 pdev = pci_find_devices(ohci_pci_ids, CONFIG_PCI_OHCI_DEVNO);
4dae14ce
ZW		 1825
1826 if (pdev != -1) {
1827 u16 vid, did;
1828 u32 base;
1829 pci_read_config_word(pdev, PCI_VENDOR_ID, &vid);
1830 pci_read_config_word(pdev, PCI_DEVICE_ID, &did);
1831 printf("OHCI pci controller (%04x, %04x) found @(%d:%d:%d)\n",
1832 vid, did, (pdev >> 16) & 0xff,
1833 (pdev >> 11) & 0x1f, (pdev >> 8) & 0x7);
1834 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &base);
1835 printf("OHCI regs address 0x%08x\n", base);
1836 gohci.regs = (struct ohci_regs *)base;
1837 } else
1838 return -1;
1839#else
24e37645 1840 gohci.regs = (struct ohci_regs *)CFG_USB_OHCI_REGS_BASE;
4dae14ce 1841#endif
3e326ece
MK		 1842
1843 gohci.flags = 0;
301f1aa3 1844 gohci.slot_name = CFG_USB_OHCI_SLOT_NAME;
3e326ece
MK		 1845
1846 if (hc_reset (&gohci) < 0) {
1847 hc_release_ohci (&gohci);
1848 err ("can't reset usb-%s", gohci.slot_name);
ddf83a2f 1849#ifdef CFG_USB_OHCI_BOARD_INIT
24e37645 1850 /* board dependant cleanup */
ddf83a2f 1851 usb_board_init_fail();
24e37645
MK		 1852#endif
1853
ddf83a2f 1854#ifdef CFG_USB_OHCI_CPU_INIT
24e37645 1855 /* cpu dependant cleanup */
ddf83a2f 1856 usb_cpu_init_fail();
24e37645 1857#endif
3e326ece
MK		 1858 return -1;
1859 }
1860
1861 /* FIXME this is a second HC reset; why?? */
1862 /* writel(gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1863 wait_ms(10); */
3e326ece
MK		 1864 if (hc_start (&gohci) < 0) {
1865 err ("can't start usb-%s", gohci.slot_name);
1866 hc_release_ohci (&gohci);
1867 /* Initialization failed */
ddf83a2f 1868#ifdef CFG_USB_OHCI_BOARD_INIT
24e37645
MK		 1869 /* board dependant cleanup */
1870 usb_board_stop();
1871#endif
1872
ddf83a2f 1873#ifdef CFG_USB_OHCI_CPU_INIT
24e37645
MK		 1874 /* cpu dependant cleanup */
1875 usb_cpu_stop();
1876#endif
3e326ece
MK		 1877 return -1;
1878 }
1879
1880#ifdef DEBUG
1881 ohci_dump (&gohci, 1);
1882#else
1883 wait_ms(1);
1884#endif
1885 ohci_inited = 1;
1886 return 0;
1887}
1888
1889int usb_lowlevel_stop(void)
1890{
1891 /* this gets called really early - before the controller has */
1892 /* even been initialized! */
1893 if (!ohci_inited)
1894 return 0;
1895 /* TODO release any interrupts, etc. */
1896 /* call hc_release_ohci() here ? */
1897 hc_reset (&gohci);
1898
ddf83a2f 1899#ifdef CFG_USB_OHCI_BOARD_INIT
3e326ece
MK		 1900 /* board dependant cleanup */
1901 if(usb_board_stop())
1902 return -1;
24e37645
MK		 1903#endif
1904
ddf83a2f 1905#ifdef CFG_USB_OHCI_CPU_INIT
24e37645
MK		 1906 /* cpu dependant cleanup */
1907 if(usb_cpu_stop())
1908 return -1;
1909#endif
3e326ece
MK		 1910
1911 return 0;
1912}
7b59b3c7 1913#endif /* CONFIG_USB_OHCI_NEW */
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